Lines Matching +full:enable +full:- +full:remote +full:- +full:sense
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2007 Renesas Solutions Corp.
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
26 #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
28 #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
30 #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
31 #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
32 #define M66592_USBE 0x0001 /* b0: USB module operation enable */
35 #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
42 #define M66592_WKUP 0x0100 /* b8: Remote wakeup */
43 #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */
44 #define M66592_USBRST 0x0040 /* b6: USB reset enable */
45 #define M66592_RESUME 0x0020 /* b5: Resume enable */
46 #define M66592_UACT 0x0010 /* b4: USB bus enable */
47 #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
48 #define M66592_HSMODE 0x0003 /* Hi-Speed mode */
49 #define M66592_FSMODE 0x0002 /* Full-Speed mode */
53 #define M66592_UTST 0x000F /* b4-0: Test select */
65 /* built-in registers */
79 #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */
87 #define M66592_DENDE 0x0010 /* b4: Dend enable */
101 #define M66592_DREQE 0x1000 /* b12: DREQ output enable */
105 #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
107 #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
109 #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
117 #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */
126 #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */
148 #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */
152 #define M66592_INTL 0x0002 /* b1: Interrupt sense select */
153 #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */
189 #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */
204 #define M66592_DVSQ 0x0070 /* b6-4: Device state */
214 #define M66592_DVSQS 0x0030 /* b5-4: Device state */
216 #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
227 #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */
235 #define M66592_FRNM 0x07FF /* b10-0: Frame number */
238 #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */
246 #define M66592_USBADDR 0x007F /* b6-0: USB address */
249 #define M66592_bRequest 0xFF00 /* b15-8: bRequest */
263 #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
267 #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
271 #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */
277 #define M66592_wValue 0xFFFF /* b15-0: wValue */
298 #define M66592_wIndex 0xFFFF /* b15-0: wIndex */
299 #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */
307 #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */
313 #define M66592_wLength 0xFFFF /* b15-0: wLength */
320 #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */
325 #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */
334 #define M66592_PID 0x0003 /* b1-0: Response PID */
340 #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */
351 #define M66592_TYP 0xC000 /* b15-14: Transfer type */
364 #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */
382 #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
383 #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
384 #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */
387 #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
390 #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */
391 #define M66592_IITV 0x0007 /* b2-0: ISO interval */
401 #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */
406 #define M66592_PID 0x0003 /* b1-0: Response PID */
411 #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
495 #define m66592_to_gadget(m66592) (&m66592->gadget)
520 /*-------------------------------------------------------------------------*/
523 return ioread16(m66592->reg + offset); in m66592_read()
530 void __iomem *fifoaddr = m66592->reg + offset; in m66592_read_fifo()
532 if (m66592->pdata->on_chip) { in m66592_read_fifo()
544 iowrite16(val, m66592->reg + offset); in m66592_write()
566 void __iomem *fifoaddr = m66592->reg + ep->fifoaddr; in m66592_write_fifo()
568 if (m66592->pdata->on_chip) { in m66592_write_fifo()
580 iowrite8(pb[i], fifoaddr + (3 - i)); in m66592_write_fifo()
592 if (m66592->pdata->wr0_shorted_to_wr1) in m66592_write_fifo()
593 m66592_bclr(m66592, M66592_MBW_16, ep->fifosel); in m66592_write_fifo()
595 if (m66592->pdata->wr0_shorted_to_wr1) in m66592_write_fifo()
596 m66592_bset(m66592, M66592_MBW_16, ep->fifosel); in m66592_write_fifo()