Lines Matching +full:endpoint +full:- +full:base
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
23 * @rxbc: receive (OUT) 0 endpoint byte count register.
24 * @txbc: transmit (IN) 0 endpoint byte count register.
25 * @cs: 0 endpoint control and status register.
27 * @fifo: 0 endpoint fifo register.
31 * @maxpack: 0 endpoint max packet size.
45 /* EP0CS - bitmasks. */
46 /* Endpoint 0 stall bit for status stage. */
50 /* IN 0 endpoint busy bit. */
52 /* OUT 0 endpoint busy bit. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
71 * @rxbc: OUT endpoint byte count register.
72 * @rxcon: OUT endpoint control register.
73 * @rxcs: OUT endpoint control and status register.
74 * @txbc: IN endpoint byte count register.
75 * @txcon: IN endpoint control register.
76 * @txcs: IN endpoint control and status register.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
90 /* Endpoint type. */
92 /* Endpoint type: isochronous. */
94 /* Endpoint type: bulk. */
96 /* Endpoint type: interrupt. */
101 /* Endpoint stall bit. */
103 /* Endpoint enable bit.*/
106 /* rxcs/txcs - endpoint control and status bitmasks. */
107 /* Data sequence error for the ISO endpoint. */
111 * struct cdns2_epx_regs - endpoint 1..15 related registers.
115 * @endprst: endpoint reset register.
117 * @isoautoarm: ISO auto-arm register.
125 * @rxstaddr: receive (OUT) start address endpoint buffer register.
127 * @txstaddr: transmit (IN) start address endpoint buffer register.
152 /* ENDPRST - bitmasks. */
153 /* Endpoint number. */
165 * struct cdns2_interrupt_regs - USB interrupt related registers.
188 /* EXTIRQ and EXTIEN - bitmasks. */
196 /* USBIEN and USBIRQ - bitmasks. */
199 /* Start-of-frame interrupt bit. */
207 /* USB high-speed mode interrupt bit. */
215 * struct cdns2_usb_regs - USB controller registers.
220 * @endprst: endpoint reset register.
248 /* LPMCTRL - bitmasks. */
256 /* LPMCLOCK - bitmasks. */
264 /* USBCS - bitmasks. */
267 /* Remote wake-up bit. */
274 /* FIFOCTRL - bitmasks. */
275 /* Endpoint number. */
286 /* SPEEDCTRL - bitmasks. */
294 /* CPUCTRL- bitmasks. */
308 * struct cdns2_adma_regs - ADMA controller registers.
312 * @ep_sel: DMA endpoint select register.
313 * @ep_traddr: DMA endpoint transfer ring address register.
314 * @ep_cfg: DMA endpoint configuration register.
315 * @ep_cmd: DMA endpoint command register.
316 * @ep_sts: DMA endpoint status register.
318 * @ep_sts_en: DMA endpoint status enable register.
320 * @ep_ien: DMA endpoint interrupt enable register.
321 * @ep_ists: DMA endpoint interrupt status register.
355 /* DMA_CONF - bitmasks. */
363 /* DMA_EP_CFG - bitmasks. */
364 /* Endpoint enable. */
367 /* DMA_EP_CMD - bitmasks. */
368 /* Endpoint reset. */
375 /* DMA_EP_STS - bitmasks. */
393 /* DMA_EP_STS_EN - bitmasks. */
403 /* DMA_EP_IEN - bitmasks. */
408 /* DMA_EP_ISTS - bitmasks. */
414 #define ep_to_cdns2_ep(ep) (container_of(ep, struct cdns2_endpoint, endpoint))
416 /*-------------------------------------------------------------------------*/
428 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_ISO_BUFF_SIZE - \
429 ((addr) & (TRB_MAX_ISO_BUFF_SIZE - 1)))
436 * struct cdns2_trb - represent Transfer Descriptor block.
468 /* Cycle bit - indicates TRB ownership by driver or hw. */
489 /*-------------------------------------------------------------------------*/
500 /*-------------------------------------------------------------------------*/
506 * struct cdns2_ring - transfer ring representation.
526 * struct cdns2_endpoint - extended device side representation of USB endpoint.
527 * @endpoint: usb endpoint.
530 * @pdev: device associated with endpoint.
532 * @ring: transfer ring associated with endpoint.
533 * @ep_state: state of endpoint.
534 * @idx: index of endpoint in pdev->eps table.
535 * @dir: endpoint direction.
536 * @num: endpoint number (1 - 15).
538 * @interval: interval between packets used for ISOC and Interrupt endpoint.
539 * @buffering: on-chip buffers assigned to endpoint.
541 * @skip: Sometimes the controller cannot process isochronous endpoint ring
545 * process the missed TDs on the endpoint ring.
552 struct usb_ep endpoint; member
587 * struct cdns2_request - extended device side representation of usb_request
617 * struct cdns2_device - represent USB device.
623 * @regs: base address for registers
624 * @usb_regs: base address for common USB registers.
625 * @ep0_regs: base address for endpoint 0 related registers.
626 * @epx_regs: base address for all none control endpoint registers.
627 * @interrupt_regs: base address for interrupt handling related registers.
628 * @adma_regs: base address for ADMA registers.
629 * @eps_dma_pool: endpoint Transfer Ring pool.
636 * @selected_ep: actually selected endpoint. It's used only to improve
646 * bit: 0 - ep0, 1 - epOut1, 2 - epIn1, 3 - epOut2 ...
648 * @onchip_tx_buf: size of transmit on-chip buffer in KB.
649 * @onchip_rx_buf: size of receive on-chip buffer in KB.
656 /* generic spin-lock for drivers */
688 ((pdev)->eps_supported & \