Lines Matching +full:g12a +full:- +full:usb3 +full:- +full:pcie +full:- +full:phy

1 # SPDX-License-Identifier: GPL-2.0
4 	tristate "DesignWare USB3 DRD Core Support"
11 	  USB controller based on the DesignWare USB3 IP Core.
19 	bool "Register ULPI PHY Interface"
22 	  Select this if you have ULPI type PHY attached to your DWC3
74 	  Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
78 	tristate "PCIe-based Platforms"
82 	  If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 	tristate "Synopsys PCIe-based HAPS Platforms"
90 	  If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
102 	tristate "Amlogic Meson G12A Platforms"
109 	  Support USB2/3 functionality in Amlogic G12A platforms.
118 	  Currently supports Xilinx and Qualcomm DWC USB3 IP.
126 	  STMicroelectronics SoCs with one DesignWare Core USB3 IP
158 	  Support Xilinx SoCs with DesignWare Core USB3 IP.
167 	  Support TI's AM62 platforms with DesignWare Core USB3 IP.
168 	  The Designware Core USB3 IP is programmed to operate in
177 	  Support Cavium Octeon platforms with DesignWare Core USB3 IP.
187 	  RTK DHC RTD SoCs with DesignWare Core USB3 IP inside,
189 	  or dual-role mode.