Lines Matching +full:hardware +full:- +full:fifo
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
20 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
22 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
23 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
24 p->max_packet_count = 511; in dwc2_set_bcm_params()
25 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
30 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
32 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
33 p->otg_caps.srp_support = false; in dwc2_set_his_params()
34 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_his_params()
35 p->host_rx_fifo_size = 512; in dwc2_set_his_params()
36 p->host_nperio_tx_fifo_size = 512; in dwc2_set_his_params()
37 p->host_perio_tx_fifo_size = 512; in dwc2_set_his_params()
38 p->max_transfer_size = 65535; in dwc2_set_his_params()
39 p->max_packet_count = 511; in dwc2_set_his_params()
40 p->host_channels = 16; in dwc2_set_his_params()
41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_his_params()
42 p->phy_utmi_width = 8; in dwc2_set_his_params()
43 p->i2c_enable = false; in dwc2_set_his_params()
44 p->reload_ctl = false; in dwc2_set_his_params()
45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_his_params()
47 p->change_speed_quirk = true; in dwc2_set_his_params()
48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_his_params()
53 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_jz4775_params()
55 p->otg_caps.hnp_support = false; in dwc2_set_jz4775_params()
56 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_jz4775_params()
57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_jz4775_params()
58 p->phy_utmi_width = 16; in dwc2_set_jz4775_params()
59 p->activate_ingenic_overcurrent_detection = in dwc2_set_jz4775_params()
60 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_jz4775_params()
65 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_loongson_params()
67 p->phy_utmi_width = 8; in dwc2_set_loongson_params()
68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; in dwc2_set_loongson_params()
73 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x1600_params()
75 p->otg_caps.hnp_support = false; in dwc2_set_x1600_params()
76 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x1600_params()
77 p->host_channels = 16; in dwc2_set_x1600_params()
78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x1600_params()
79 p->phy_utmi_width = 16; in dwc2_set_x1600_params()
80 p->activate_ingenic_overcurrent_detection = in dwc2_set_x1600_params()
81 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x1600_params()
86 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x2000_params()
88 p->otg_caps.hnp_support = false; in dwc2_set_x2000_params()
89 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x2000_params()
90 p->host_rx_fifo_size = 1024; in dwc2_set_x2000_params()
91 p->host_nperio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
92 p->host_perio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
93 p->host_channels = 16; in dwc2_set_x2000_params()
94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x2000_params()
95 p->phy_utmi_width = 16; in dwc2_set_x2000_params()
96 p->activate_ingenic_overcurrent_detection = in dwc2_set_x2000_params()
97 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x2000_params()
102 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_s3c6400_params()
104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_s3c6400_params()
105 p->no_clock_gating = true; in dwc2_set_s3c6400_params()
106 p->phy_utmi_width = 8; in dwc2_set_s3c6400_params()
111 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_socfpga_agilex_params()
113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_socfpga_agilex_params()
114 p->no_clock_gating = true; in dwc2_set_socfpga_agilex_params()
119 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_rk_params()
121 p->otg_caps.hnp_support = false; in dwc2_set_rk_params()
122 p->otg_caps.srp_support = false; in dwc2_set_rk_params()
123 p->host_rx_fifo_size = 525; in dwc2_set_rk_params()
124 p->host_nperio_tx_fifo_size = 128; in dwc2_set_rk_params()
125 p->host_perio_tx_fifo_size = 256; in dwc2_set_rk_params()
126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_rk_params()
128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_rk_params()
129 p->lpm = false; in dwc2_set_rk_params()
130 p->lpm_clock_gating = false; in dwc2_set_rk_params()
131 p->besl = false; in dwc2_set_rk_params()
132 p->hird_threshold_en = false; in dwc2_set_rk_params()
133 p->no_clock_gating = true; in dwc2_set_rk_params()
138 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_danube_params()
140 p->otg_caps.hnp_support = false; in dwc2_set_ltq_danube_params()
141 p->otg_caps.srp_support = false; in dwc2_set_ltq_danube_params()
146 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_ase_params()
148 p->otg_caps.hnp_support = false; in dwc2_set_ltq_ase_params()
149 p->otg_caps.srp_support = false; in dwc2_set_ltq_ase_params()
150 p->host_rx_fifo_size = 288; in dwc2_set_ltq_ase_params()
151 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_ase_params()
152 p->host_perio_tx_fifo_size = 96; in dwc2_set_ltq_ase_params()
153 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_ltq_ase_params()
159 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_xrx200_params()
161 p->otg_caps.hnp_support = false; in dwc2_set_ltq_xrx200_params()
162 p->otg_caps.srp_support = false; in dwc2_set_ltq_xrx200_params()
163 p->host_rx_fifo_size = 288; in dwc2_set_ltq_xrx200_params()
164 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_xrx200_params()
165 p->host_perio_tx_fifo_size = 136; in dwc2_set_ltq_xrx200_params()
170 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_params()
172 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_params()
173 p->otg_caps.srp_support = false; in dwc2_set_amlogic_params()
174 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_params()
175 p->host_rx_fifo_size = 512; in dwc2_set_amlogic_params()
176 p->host_nperio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
177 p->host_perio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
178 p->host_channels = 16; in dwc2_set_amlogic_params()
179 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_params()
180 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << in dwc2_set_amlogic_params()
182 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_amlogic_params()
187 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_g12a_params()
189 p->lpm = false; in dwc2_set_amlogic_g12a_params()
190 p->lpm_clock_gating = false; in dwc2_set_amlogic_g12a_params()
191 p->besl = false; in dwc2_set_amlogic_g12a_params()
192 p->hird_threshold_en = false; in dwc2_set_amlogic_g12a_params()
197 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_a1_params()
199 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_a1_params()
200 p->otg_caps.srp_support = false; in dwc2_set_amlogic_a1_params()
201 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_a1_params()
202 p->host_rx_fifo_size = 192; in dwc2_set_amlogic_a1_params()
203 p->host_nperio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
204 p->host_perio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
205 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_a1_params()
206 p->phy_utmi_width = 8; in dwc2_set_amlogic_a1_params()
207 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amlogic_a1_params()
208 p->lpm = false; in dwc2_set_amlogic_a1_params()
209 p->lpm_clock_gating = false; in dwc2_set_amlogic_a1_params()
210 p->besl = false; in dwc2_set_amlogic_a1_params()
211 p->hird_threshold_en = false; in dwc2_set_amlogic_a1_params()
216 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amcc_params()
218 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amcc_params()
223 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_cv1800_params()
225 p->otg_caps.hnp_support = false; in dwc2_set_cv1800_params()
226 p->otg_caps.srp_support = false; in dwc2_set_cv1800_params()
227 p->host_dma = false; in dwc2_set_cv1800_params()
228 p->g_dma = false; in dwc2_set_cv1800_params()
229 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_cv1800_params()
230 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_cv1800_params()
231 p->phy_utmi_width = 16; in dwc2_set_cv1800_params()
232 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_cv1800_params()
233 p->lpm = false; in dwc2_set_cv1800_params()
234 p->lpm_clock_gating = false; in dwc2_set_cv1800_params()
235 p->besl = false; in dwc2_set_cv1800_params()
236 p->hird_threshold_en = false; in dwc2_set_cv1800_params()
237 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_cv1800_params()
242 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f4x9_fsotg_params()
244 p->otg_caps.hnp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
245 p->otg_caps.srp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
246 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32f4x9_fsotg_params()
247 p->host_rx_fifo_size = 128; in dwc2_set_stm32f4x9_fsotg_params()
248 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
249 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
250 p->max_packet_count = 256; in dwc2_set_stm32f4x9_fsotg_params()
251 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32f4x9_fsotg_params()
252 p->i2c_enable = false; in dwc2_set_stm32f4x9_fsotg_params()
253 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32f4x9_fsotg_params()
258 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f7_hsotg_params()
260 p->host_rx_fifo_size = 622; in dwc2_set_stm32f7_hsotg_params()
261 p->host_nperio_tx_fifo_size = 128; in dwc2_set_stm32f7_hsotg_params()
262 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32f7_hsotg_params()
267 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_fsotg_params()
269 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_fsotg_params()
270 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_fsotg_params()
271 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_fsotg_params()
272 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32mp15_fsotg_params()
273 p->host_rx_fifo_size = 128; in dwc2_set_stm32mp15_fsotg_params()
274 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
275 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
276 p->max_packet_count = 256; in dwc2_set_stm32mp15_fsotg_params()
277 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32mp15_fsotg_params()
278 p->i2c_enable = false; in dwc2_set_stm32mp15_fsotg_params()
279 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32mp15_fsotg_params()
280 p->activate_stm_id_vb_detection = true; in dwc2_set_stm32mp15_fsotg_params()
281 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_fsotg_params()
282 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_fsotg_params()
283 p->host_support_fs_ls_low_power = true; in dwc2_set_stm32mp15_fsotg_params()
284 p->host_ls_low_power_phy_clk = true; in dwc2_set_stm32mp15_fsotg_params()
289 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_hsotg_params()
291 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_hsotg_params()
292 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_hsotg_params()
293 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_hsotg_params()
294 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); in dwc2_set_stm32mp15_hsotg_params()
295 p->host_rx_fifo_size = 440; in dwc2_set_stm32mp15_hsotg_params()
296 p->host_nperio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
297 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
298 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_hsotg_params()
299 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_hsotg_params()
300 p->lpm = false; in dwc2_set_stm32mp15_hsotg_params()
301 p->lpm_clock_gating = false; in dwc2_set_stm32mp15_hsotg_params()
302 p->besl = false; in dwc2_set_stm32mp15_hsotg_params()
303 p->hird_threshold_en = false; in dwc2_set_stm32mp15_hsotg_params()
307 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
308 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
309 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
310 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
311 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
312 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
313 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
314 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
315 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
316 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
317 { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
318 { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
319 { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
320 { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
321 { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
323 { .compatible = "samsung,s3c6400-hsotg",
325 { .compatible = "amlogic,meson8-usb",
327 { .compatible = "amlogic,meson8b-usb",
329 { .compatible = "amlogic,meson-gxbb-usb",
331 { .compatible = "amlogic,meson-g12a-usb",
333 { .compatible = "amlogic,meson-a1-usb",
335 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
336 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
337 { .compatible = "sophgo,cv1800-usb",
339 { .compatible = "st,stm32f4x9-fsotg",
341 { .compatible = "st,stm32f4x9-hsotg" },
342 { .compatible = "st,stm32f7-hsotg",
344 { .compatible = "st,stm32mp15-fsotg",
346 { .compatible = "st,stm32mp15-hsotg",
348 { .compatible = "intel,socfpga-agilex-hsotg",
355 /* This ID refers to the same USB IP as of_device_id brcm,bcm2835-usb */
380 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
382 hsotg->params.otg_caps.hnp_support = true; in dwc2_set_param_otg_cap()
383 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
388 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
389 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
392 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
393 hsotg->params.otg_caps.srp_support = false; in dwc2_set_param_otg_cap()
401 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
413 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_param_phy_type()
415 hsotg->params.phy_type = val; in dwc2_set_param_phy_type()
422 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
431 hsotg->params.speed = val; in dwc2_set_param_speed()
438 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
441 if (hsotg->phy) { in dwc2_set_param_phy_utmi_width()
444 * width is 8-bit and set the phyif appropriately. in dwc2_set_param_phy_utmi_width()
446 if (phy_get_bus_width(hsotg->phy) == 8) in dwc2_set_param_phy_utmi_width()
450 hsotg->params.phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
455 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_tx_fifo_sizes()
462 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); in dwc2_set_param_tx_fifo_sizes()
465 p->g_tx_fifo_size[i] = depth_average; in dwc2_set_param_tx_fifo_sizes()
472 if (hsotg->hw_params.hibernation) in dwc2_set_param_power_down()
474 else if (hsotg->hw_params.power_optimized) in dwc2_set_param_power_down()
479 hsotg->params.power_down = val; in dwc2_set_param_power_down()
484 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_lpm()
486 p->lpm = hsotg->hw_params.lpm_mode; in dwc2_set_param_lpm()
487 if (p->lpm) { in dwc2_set_param_lpm()
488 p->lpm_clock_gating = true; in dwc2_set_param_lpm()
489 p->besl = true; in dwc2_set_param_lpm()
490 p->hird_threshold_en = true; in dwc2_set_param_lpm()
491 p->hird_threshold = 4; in dwc2_set_param_lpm()
493 p->lpm_clock_gating = false; in dwc2_set_param_lpm()
494 p->besl = false; in dwc2_set_param_lpm()
495 p->hird_threshold_en = false; in dwc2_set_param_lpm()
500 * dwc2_set_default_params() - Set all core parameters to their
501 * auto-detected default values.
508 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_set_default_params()
509 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_default_params()
510 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_set_default_params()
518 p->phy_ulpi_ddr = false; in dwc2_set_default_params()
519 p->phy_ulpi_ext_vbus = false; in dwc2_set_default_params()
520 p->eusb2_disc = false; in dwc2_set_default_params()
522 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; in dwc2_set_default_params()
523 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; in dwc2_set_default_params()
524 p->i2c_enable = hw->i2c_enable; in dwc2_set_default_params()
525 p->acg_enable = hw->acg_enable; in dwc2_set_default_params()
526 p->ulpi_fs_ls = false; in dwc2_set_default_params()
527 p->ts_dline = false; in dwc2_set_default_params()
528 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); in dwc2_set_default_params()
529 p->uframe_sched = true; in dwc2_set_default_params()
530 p->external_id_pin_ctl = false; in dwc2_set_default_params()
531 p->ipg_isoc_en = false; in dwc2_set_default_params()
532 p->service_interval = false; in dwc2_set_default_params()
533 p->max_packet_count = hw->max_packet_count; in dwc2_set_default_params()
534 p->max_transfer_size = hw->max_transfer_size; in dwc2_set_default_params()
535 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_default_params()
536 p->ref_clk_per = 33333; in dwc2_set_default_params()
537 p->sof_cnt_wkup_alert = 100; in dwc2_set_default_params()
539 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_set_default_params()
540 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
541 p->host_dma = dma_capable; in dwc2_set_default_params()
542 p->dma_desc_enable = false; in dwc2_set_default_params()
543 p->dma_desc_fs_enable = false; in dwc2_set_default_params()
544 p->host_support_fs_ls_low_power = false; in dwc2_set_default_params()
545 p->host_ls_low_power_phy_clk = false; in dwc2_set_default_params()
546 p->host_channels = hw->host_channels; in dwc2_set_default_params()
547 p->host_rx_fifo_size = hw->rx_fifo_size; in dwc2_set_default_params()
548 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; in dwc2_set_default_params()
549 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; in dwc2_set_default_params()
552 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_set_default_params()
553 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
554 p->g_dma = dma_capable; in dwc2_set_default_params()
555 p->g_dma_desc = hw->dma_desc_enable; in dwc2_set_default_params()
560 * gadget driver. These defaults have been hard-coded in dwc2_set_default_params()
563 * auto-detect if the hardware does not support the in dwc2_set_default_params()
566 p->g_rx_fifo_size = 2048; in dwc2_set_default_params()
567 p->g_np_tx_fifo_size = 1024; in dwc2_set_default_params()
573 * dwc2_get_device_properties() - Read in device properties.
581 struct dwc2_core_params *p = &hsotg->params; in dwc2_get_device_properties()
584 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_get_device_properties()
585 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_get_device_properties()
586 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", in dwc2_get_device_properties()
587 &p->g_rx_fifo_size); in dwc2_get_device_properties()
589 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", in dwc2_get_device_properties()
590 &p->g_np_tx_fifo_size); in dwc2_get_device_properties()
592 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); in dwc2_get_device_properties()
595 memset(p->g_tx_fifo_size, 0, in dwc2_get_device_properties()
596 sizeof(p->g_tx_fifo_size)); in dwc2_get_device_properties()
597 device_property_read_u32_array(hsotg->dev, in dwc2_get_device_properties()
598 "g-tx-fifo-size", in dwc2_get_device_properties()
599 &p->g_tx_fifo_size[1], in dwc2_get_device_properties()
603 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); in dwc2_get_device_properties()
606 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); in dwc2_get_device_properties()
613 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
615 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_check_param_otg_cap()
617 } else if (!hsotg->params.otg_caps.hnp_support) { in dwc2_check_param_otg_cap()
619 if (hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
620 switch (hsotg->hw_params.op_mode) { in dwc2_check_param_otg_cap()
646 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_check_param_phy_type()
647 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_check_param_phy_type()
649 switch (hsotg->params.phy_type) { in dwc2_check_param_phy_type()
675 int phy_type = hsotg->params.phy_type; in dwc2_check_param_speed()
676 int speed = hsotg->params.speed; in dwc2_check_param_speed()
680 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && in dwc2_check_param_speed()
699 int param = hsotg->params.phy_utmi_width; in dwc2_check_param_phy_utmi_width()
700 int width = hsotg->hw_params.utmi_phy_data_width; in dwc2_check_param_phy_utmi_width()
720 int param = hsotg->params.power_down; in dwc2_check_param_power_down()
726 if (hsotg->hw_params.power_optimized) in dwc2_check_param_power_down()
728 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
733 if (hsotg->hw_params.hibernation) in dwc2_check_param_power_down()
735 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
740 dev_err(hsotg->dev, in dwc2_check_param_power_down()
747 hsotg->params.power_down = param; in dwc2_check_param_power_down()
753 int fifo; in dwc2_check_param_tx_fifo_sizes() local
759 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; in dwc2_check_param_tx_fifo_sizes()
761 for (fifo = 1; fifo <= fifo_count; fifo++) in dwc2_check_param_tx_fifo_sizes()
762 total += hsotg->params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
765 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", in dwc2_check_param_tx_fifo_sizes()
770 for (fifo = 1; fifo <= fifo_count; fifo++) { in dwc2_check_param_tx_fifo_sizes()
771 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
773 if (hsotg->params.g_tx_fifo_size[fifo] < min || in dwc2_check_param_tx_fifo_sizes()
774 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { in dwc2_check_param_tx_fifo_sizes()
775 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", in dwc2_check_param_tx_fifo_sizes()
776 __func__, fifo, in dwc2_check_param_tx_fifo_sizes()
777 hsotg->params.g_tx_fifo_size[fifo]); in dwc2_check_param_tx_fifo_sizes()
778 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; in dwc2_check_param_tx_fifo_sizes()
787 if (!hsotg->params.eusb2_disc) in dwc2_check_param_eusb2_disc()
797 hsotg->params.eusb2_disc = false; in dwc2_check_param_eusb2_disc()
803 if ((int)(hsotg->params._param) < (_min) || \
804 (hsotg->params._param) > (_max)) { \
805 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
806 __func__, #_param, hsotg->params._param); \
807 hsotg->params._param = (_def); \
812 if (hsotg->params._param && !(_check)) { \
813 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
814 __func__, #_param, hsotg->params._param); \
815 hsotg->params._param = false; \
821 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_check_params()
822 struct dwc2_core_params *p = &hsotg->params; in dwc2_check_params()
823 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_check_params()
832 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); in dwc2_check_params()
833 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); in dwc2_check_params()
834 CHECK_BOOL(i2c_enable, hw->i2c_enable); in dwc2_check_params()
835 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); in dwc2_check_params()
836 CHECK_BOOL(acg_enable, hw->acg_enable); in dwc2_check_params()
837 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); in dwc2_check_params()
838 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); in dwc2_check_params()
839 CHECK_BOOL(lpm, hw->lpm_mode); in dwc2_check_params()
840 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); in dwc2_check_params()
841 CHECK_BOOL(besl, hsotg->params.lpm); in dwc2_check_params()
842 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); in dwc2_check_params()
843 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); in dwc2_check_params()
844 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); in dwc2_check_params()
845 CHECK_BOOL(service_interval, hw->service_interval_mode); in dwc2_check_params()
847 15, hw->max_packet_count, in dwc2_check_params()
848 hw->max_packet_count); in dwc2_check_params()
850 2047, hw->max_transfer_size, in dwc2_check_params()
851 hw->max_transfer_size); in dwc2_check_params()
853 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_check_params()
854 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
856 CHECK_BOOL(dma_desc_enable, p->host_dma); in dwc2_check_params()
857 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); in dwc2_check_params()
859 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); in dwc2_check_params()
861 1, hw->host_channels, in dwc2_check_params()
862 hw->host_channels); in dwc2_check_params()
864 16, hw->rx_fifo_size, in dwc2_check_params()
865 hw->rx_fifo_size); in dwc2_check_params()
867 16, hw->host_nperio_tx_fifo_size, in dwc2_check_params()
868 hw->host_nperio_tx_fifo_size); in dwc2_check_params()
870 16, hw->host_perio_tx_fifo_size, in dwc2_check_params()
871 hw->host_perio_tx_fifo_size); in dwc2_check_params()
874 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_check_params()
875 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
877 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); in dwc2_check_params()
879 16, hw->rx_fifo_size, in dwc2_check_params()
880 hw->rx_fifo_size); in dwc2_check_params()
882 16, hw->dev_nperio_tx_fifo_size, in dwc2_check_params()
883 hw->dev_nperio_tx_fifo_size); in dwc2_check_params()
889 * Gets host hardware parameters. Forces host mode if not currently in
895 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_host_hwparams()
899 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) in dwc2_get_host_hwparams()
907 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
909 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
914 * Gets device hardware parameters. Forces device mode if not
920 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_dev_hwparams()
922 int fifo, fifo_count; in dwc2_get_dev_hwparams() local
924 if (hsotg->dr_mode == USB_DR_MODE_HOST) in dwc2_get_dev_hwparams()
933 for (fifo = 1; fifo <= fifo_count; fifo++) { in dwc2_get_dev_hwparams()
934 hw->g_tx_fifo_size[fifo] = in dwc2_get_dev_hwparams()
935 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & in dwc2_get_dev_hwparams()
939 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_dev_hwparams()
944 * dwc2_get_hwparams() - During device initialization, read various hardware
952 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
964 hw->dev_ep_dirs = hwcfg1; in dwc2_get_hwparams()
967 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> in dwc2_get_hwparams()
969 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> in dwc2_get_hwparams()
971 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); in dwc2_get_hwparams()
972 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> in dwc2_get_hwparams()
974 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
976 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
978 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> in dwc2_get_hwparams()
980 hw->nperio_tx_q_depth = in dwc2_get_hwparams()
983 hw->host_perio_tx_q_depth = in dwc2_get_hwparams()
986 hw->dev_token_q_depth = in dwc2_get_hwparams()
993 hw->max_transfer_size = (1 << (width + 11)) - 1; in dwc2_get_hwparams()
996 hw->max_packet_count = (1 << (width + 4)) - 1; in dwc2_get_hwparams()
997 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); in dwc2_get_hwparams()
998 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> in dwc2_get_hwparams()
1000 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); in dwc2_get_hwparams()
1003 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); in dwc2_get_hwparams()
1004 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> in dwc2_get_hwparams()
1006 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> in dwc2_get_hwparams()
1008 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); in dwc2_get_hwparams()
1009 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); in dwc2_get_hwparams()
1010 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); in dwc2_get_hwparams()
1011 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> in dwc2_get_hwparams()
1013 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); in dwc2_get_hwparams()
1014 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); in dwc2_get_hwparams()
1015 hw->service_interval_mode = !!(hwcfg4 & in dwc2_get_hwparams()
1018 /* fifo sizes */ in dwc2_get_hwparams()
1019 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> in dwc2_get_hwparams()
1022 * Host specific hardware parameters. Reading these parameters in dwc2_get_hwparams()
1041 set_params = device_get_match_data(hsotg->dev); in dwc2_init_params()
1046 pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent)); in dwc2_init_params()
1048 if (pmatch && pmatch->driver_data) { in dwc2_init_params()
1049 set_params = (set_params_cb)pmatch->driver_data; in dwc2_init_params()