Lines Matching full:section
18 #define TA_WAIT_VRISE (100) /* a_wait_vrise: section 7.1.2
19 * a_wait_vrise_tmr: section 7.4.5.1
20 * TA_VBUS_RISE <= 100ms, section 4.4
25 #define TA_WAIT_VFALL (1000) /* a_wait_vfall: section 7.1.7
26 * a_wait_vfall_tmr: section: 7.4.5.2
29 #define TA_WAIT_BCON (10000) /* a_wait_bcon: section 7.1.3
31 * and 30000 ms, section 5.5, Table 5-1
34 #define TA_AIDL_BDIS (5000) /* a_suspend min 200 ms, section 5.2.1
35 * TA_AIDL_BDIS: section 5.5, Table 5-1
38 #define TA_BIDL_ADIS (500) /* TA_BIDL_ADIS: section 5.2.1
49 * section:5.1.3
53 * section:5.1.6
56 #define TB_ASE0_BRST (155) /* minimum 155 ms, section:5.3.1 */
58 #define TB_SE0_SRP (1000) /* b_idle,minimum 1s, section:5.1.2 */
60 #define TB_SSEND_SRP (1500) /* minimum 1.5 sec, section:5.1.2 */
62 #define TB_AIDL_BDIS (20) /* 4ms ~ 150ms, section 5.2.1 */