Lines Matching +full:endpoint +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
24 #include "gadget-export.h"
26 #include "cdnsp-gadget.h"
27 #include "cdnsp-trace.h"
55 /* Save read-only status and port state. */
60 * cdnsp_find_next_ext_cap - Find the offset of the extended capabilities
62 * @base: PCI MMIO registers base address.
71 int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id)
78 val = readl(base + HCC_PARAMS_OFFSET);
88 val = readl(base + offset);
117 if (pdev->active_port)
118 port_num = pdev->active_port->port_num;
145 void __iomem *base;
148 base = &pdev->cap_regs->hc_capbase;
149 offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP);
150 reg = base + offset + REG_CHICKEN_BITS_2_OFFSET;
159 void __iomem *base;
162 base = &pdev->cap_regs->hc_capbase;
163 offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP);
164 reg = base + offset + REG_CHICKEN_BITS_2_OFFSET;
181 halted = readl(&pdev->op_regs->status) & STS_HALT;
185 cmd = readl(&pdev->op_regs->command);
187 writel(cmd, &pdev->op_regs->command);
206 ret = readl_poll_timeout_atomic(&pdev->op_regs->status, val,
210 dev_err(pdev->dev, "ERROR: Device halt failed\n");
214 pdev->cdnsp_state |= CDNSP_STATE_HALTED;
225 dev_err(pdev->dev, "ERROR: CDNSP controller not responding\n");
226 pdev->cdnsp_state |= CDNSP_STATE_DYING;
238 temp = readl(&pdev->op_regs->command);
240 writel(temp, &pdev->op_regs->command);
242 pdev->cdnsp_state = 0;
248 ret = readl_poll_timeout_atomic(&pdev->op_regs->status, temp,
252 pdev->cdnsp_state = CDNSP_STATE_DYING;
253 dev_err(pdev->dev, "ERROR: Controller run failed\n");
272 temp = readl(&pdev->op_regs->status);
275 dev_err(pdev->dev, "Device not accessible, reset failed.\n");
276 return -ENODEV;
280 dev_err(pdev->dev, "Controller not halted, aborting reset.\n");
281 return -EINVAL;
284 command = readl(&pdev->op_regs->command);
286 writel(command, &pdev->op_regs->command);
288 ret = readl_poll_timeout_atomic(&pdev->op_regs->command, temp,
292 dev_err(pdev->dev, "ERROR: Controller reset failed\n");
300 ret = readl_poll_timeout_atomic(&pdev->op_regs->status, temp,
305 dev_err(pdev->dev, "ERROR: Controller not ready to work\n");
309 dev_dbg(pdev->dev, "Controller ready to work");
315 * cdnsp_get_endpoint_index - Find the index for an endpoint given its
318 * Index = (epnum * 2) + direction - 1,
321 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
331 return (index * 2) + (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
335 * Find the flag for this endpoint (for use in the control context). Use the
336 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
347 struct cdnsp_device *pdev = pep->pdev;
351 if (preq->epnum == 0 && !list_empty(&pep->pending_list)) {
353 return -EBUSY;
356 request = &preq->request;
357 request->actual = 0;
358 request->status = -EINPROGRESS;
359 preq->direction = pep->direction;
360 preq->epnum = pep->number;
361 preq->td.drbl = 0;
363 ret = usb_gadget_map_request_by_dev(pdev->dev, request, pep->direction);
369 list_add_tail(&preq->list, &pep->pending_list);
373 switch (usb_endpoint_type(pep->endpoint.desc)) {
391 usb_gadget_unmap_request_by_dev(pdev->dev, &preq->request,
392 pep->direction);
393 list_del(&preq->list);
400 * Remove the request's TD from the endpoint ring. This may cause the
416 * into a series of 1-TRB transfer no-op TDs. No-ops shouldn't be chained.
418 * the stop endpoint command.
420 * 3) The TD may have completed by the time the Stop Endpoint Command
426 struct cdnsp_device *pdev = pep->pdev;
432 if (GET_EP_CTX_STATE(pep->out_ctx) == EP_STATE_RUNNING)
447 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
451 * configure endpoint command will leave that endpoint's state
453 * endpoint contexts.
455 ctrl_ctx->drop_flags = 0;
456 ctrl_ctx->add_flags = 0;
457 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
458 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
460 /* Endpoint 0 is always valid */
461 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
463 ep_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, i);
464 ep_ctx->ep_info = 0;
465 ep_ctx->ep_info2 = 0;
466 ep_ctx->deq = 0;
467 ep_ctx->tx_info = 0;
471 /* Issue a configure endpoint command and wait for it to finish. */
476 cdnsp_queue_configure_endpoint(pdev, pdev->cmd.in_ctx->dma);
480 dev_err(pdev->dev,
482 return -EINVAL;
496 event = pdev->event_ring->dequeue;
497 segment = pdev->event_ring->deq_seg;
498 cycle_state = pdev->event_ring->cycle_state;
501 data = le32_to_cpu(event->trans_event.flags);
508 TRB_TO_EP_ID(data) == (pep->idx + 1)) {
510 event->trans_event.flags = cpu_to_le32(data);
515 segment = pdev->event_ring->deq_seg->next;
516 event = segment->trbs;
534 cmd_trb = pdev->cmd.command_trb;
535 pdev->cmd.status = 0;
537 trace_cdnsp_cmd_wait_for_compl(pdev->cmd_ring, &cmd_trb->generic);
539 ret = readl_poll_timeout_atomic(&pdev->op_regs->cmd_ring, val,
543 dev_err(pdev->dev, "ERR: Timeout while waiting for command\n");
544 trace_cdnsp_cmd_timeout(pdev->cmd_ring, &cmd_trb->generic);
545 pdev->cdnsp_state = CDNSP_STATE_DYING;
546 return -ETIMEDOUT;
549 event = pdev->event_ring->dequeue;
550 event_deq_seg = pdev->event_ring->deq_seg;
551 cycle_state = pdev->event_ring->cycle_state;
553 cmd_deq_dma = cdnsp_trb_virt_to_dma(pdev->cmd_ring->deq_seg, cmd_trb);
555 return -EINVAL;
558 flags = le32_to_cpu(event->event_cmd.flags);
562 return -EINVAL;
564 cmd_dma = le64_to_cpu(event->event_cmd.cmd_trb);
577 if (cdnsp_last_trb_on_ring(pdev->event_ring,
581 event_deq_seg = event_deq_seg->next;
582 event = event_deq_seg->trbs;
586 trace_cdnsp_handle_command(pdev->cmd_ring, &cmd_trb->generic);
588 pdev->cmd.status = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status));
589 if (pdev->cmd.status == COMP_SUCCESS)
592 return -pdev->cmd.status;
609 if (GET_EP_CTX_STATE(pep->out_ctx) == EP_STATE_STOPPED) {
610 cdnsp_queue_halt_endpoint(pdev, pep->idx);
615 pep->ep_state |= EP_HALTED;
617 cdnsp_queue_reset_ep(pdev, pep->idx);
620 trace_cdnsp_handle_cmd_reset_ep(pep->out_ctx);
625 pep->ep_state &= ~EP_HALTED;
627 if (pep->idx != 0 && !(pep->ep_state & EP_WEDGE))
630 pep->ep_state &= ~EP_WEDGE;
645 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
648 if (ctrl_ctx->add_flags == 0 && ctrl_ctx->drop_flags == 0)
651 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
652 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
653 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
656 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
657 for (i = CDNSP_ENDPOINTS_NUM; i >= 1; i--) {
660 if ((pdev->eps[i - 1].ring && !(ctrl_ctx->drop_flags & le32)) ||
661 (ctrl_ctx->add_flags & le32) || i == 1) {
662 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
663 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
668 ep_sts = GET_EP_CTX_STATE(pep->out_ctx);
670 if ((ctrl_ctx->add_flags != cpu_to_le32(SLOT_FLAG) &&
672 (ep_sts != EP_STATE_DISABLED && ctrl_ctx->drop_flags))
675 trace_cdnsp_configure_endpoint(cdnsp_get_slot_ctx(&pdev->out_ctx));
676 trace_cdnsp_handle_cmd_config_ep(pep->out_ctx);
686 * control endpoint. The USB core should come back and call
687 * cdnsp_setup_device(), and then re-set up the configuration.
695 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
696 slot_ctx->dev_info = 0;
697 pdev->device_address = 0;
700 slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx);
701 slot_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
705 pdev->eps[0].ep_state & EP_HALTED) {
706 cdnsp_halt_endpoint(pdev, &pdev->eps[0], 0);
711 * endpoint ep0 to the Running State.
713 pdev->eps[0].ep_state &= ~(EP_STOPPED | EP_HALTED);
714 pdev->eps[0].ep_state |= EP_ENABLED;
728 pdev->eps[i].ep_state |= EP_STOPPED | EP_UNCONFIGURED;
733 dev_err(pdev->dev, "Reset device failed with error code %d",
753 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
754 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
755 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
757 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
763 * Don't allow the call to succeed if endpoint only supports one stream
768 unsigned int num_streams = usb_ss_max_streams(pep->endpoint.comp_desc);
776 return -EINVAL;
794 cdnsp_setup_streams_ep_input_ctx(pdev, pep->in_ctx, &pep->stream_info);
796 pep->ep_state |= EP_HAS_STREAMS;
797 pep->stream_info.td_count = 0;
798 pep->stream_info.first_prime_det = 0;
801 return num_streams - 1;
812 pdev->slot_id = 0;
813 pdev->active_port = NULL;
815 trace_cdnsp_handle_cmd_disable_slot(cdnsp_get_slot_ctx(&pdev->out_ctx));
817 memset(pdev->in_ctx.bytes, 0, CDNSP_CTX_SIZE);
818 memset(pdev->out_ctx.bytes, 0, CDNSP_CTX_SIZE);
830 slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx);
831 slot_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
842 pdev->slot_id = 1;
845 trace_cdnsp_handle_cmd_enable_slot(cdnsp_get_slot_ctx(&pdev->out_ctx));
861 if (!pdev->slot_id) {
863 return -EINVAL;
866 if (!pdev->active_port->port_num)
867 return -EINVAL;
869 slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx);
870 dev_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
877 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
878 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
880 if (!slot_ctx->dev_info || dev_state == SLOT_STATE_DEFAULT) {
888 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
889 ctrl_ctx->drop_flags = 0;
893 cdnsp_queue_address_device(pdev, pdev->in_ctx.dma, setup);
897 trace_cdnsp_handle_cmd_addr_dev(cdnsp_get_slot_ctx(&pdev->out_ctx));
900 ctrl_ctx->add_flags = 0;
901 ctrl_ctx->drop_flags = 0;
910 if (pdev->active_port != &pdev->usb2_port || !pdev->gadget.lpm_capable)
917 &pdev->active_port->regs->portpmsc);
919 writel(PORT_L1S_NYET, &pdev->active_port->regs->portpmsc);
924 return readl(&pdev->run_regs->microframe_index) >> 3;
937 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT ||
938 !desc->wMaxPacketSize)
939 return -EINVAL;
942 pdev = pep->pdev;
943 pep->ep_state &= ~EP_UNCONFIGURED;
945 if (dev_WARN_ONCE(pdev->dev, pep->ep_state & EP_ENABLED,
946 "%s is already enabled\n", pep->name))
949 spin_lock_irqsave(&pdev->lock, flags);
953 dev_err(pdev->dev, "ERROR: Bad endpoint number\n");
954 ret = -EINVAL;
958 pep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
960 if (pdev->gadget.speed == USB_SPEED_FULL) {
962 pep->interval = desc->bInterval << 3;
964 pep->interval = BIT(desc->bInterval - 1) << 3;
968 if (pep->interval > BIT(12)) {
969 dev_err(pdev->dev, "bInterval %d not supported\n",
970 desc->bInterval);
971 ret = -EINVAL;
981 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
982 ctrl_ctx->add_flags = cpu_to_le32(added_ctxs);
983 ctrl_ctx->drop_flags = 0;
991 pep->ep_state |= EP_ENABLED;
992 pep->ep_state &= ~EP_STOPPED;
996 spin_unlock_irqrestore(&pdev->lock, flags);
1012 return -EINVAL;
1015 pdev = pep->pdev;
1017 spin_lock_irqsave(&pdev->lock, flags);
1019 if (!(pep->ep_state & EP_ENABLED)) {
1020 dev_err(pdev->dev, "%s is already disabled\n", pep->name);
1021 ret = -EINVAL;
1025 pep->ep_state |= EP_DIS_IN_RROGRESS;
1027 /* Endpoint was unconfigured by Reset Device command. */
1028 if (!(pep->ep_state & EP_UNCONFIGURED))
1032 while (!list_empty(&pep->pending_list)) {
1033 preq = next_request(&pep->pending_list);
1039 pep->ep_state &= ~EP_DIS_IN_RROGRESS;
1040 drop_flag = cdnsp_get_endpoint_flag(pep->endpoint.desc);
1041 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
1042 ctrl_ctx->drop_flags = cpu_to_le32(drop_flag);
1043 ctrl_ctx->add_flags = 0;
1047 if (!(pep->ep_state & EP_UNCONFIGURED))
1052 pep->ep_state &= ~(EP_ENABLED | EP_UNCONFIGURED);
1053 pep->ep_state |= EP_STOPPED;
1057 spin_unlock_irqrestore(&pdev->lock, flags);
1072 preq->epnum = pep->number;
1073 preq->pep = pep;
1077 return &preq->request;
1100 return -EINVAL;
1103 pdev = pep->pdev;
1105 if (!(pep->ep_state & EP_ENABLED)) {
1106 dev_err(pdev->dev, "%s: can't queue to disabled endpoint\n",
1107 pep->name);
1108 return -EINVAL;
1112 spin_lock_irqsave(&pdev->lock, flags);
1114 spin_unlock_irqrestore(&pdev->lock, flags);
1123 struct cdnsp_device *pdev = pep->pdev;
1127 if (request->status != -EINPROGRESS)
1130 if (!pep->endpoint.desc) {
1131 dev_err(pdev->dev,
1132 "%s: can't dequeue to disabled endpoint\n",
1133 pep->name);
1134 return -ESHUTDOWN;
1137 /* Requests has been dequeued during disabling endpoint. */
1138 if (!(pep->ep_state & EP_ENABLED))
1141 spin_lock_irqsave(&pdev->lock, flags);
1143 spin_unlock_irqrestore(&pdev->lock, flags);
1151 struct cdnsp_device *pdev = pep->pdev;
1156 spin_lock_irqsave(&pdev->lock, flags);
1158 preq = next_request(&pep->pending_list);
1162 ret = -EAGAIN;
1170 spin_unlock_irqrestore(&pdev->lock, flags);
1177 struct cdnsp_device *pdev = pep->pdev;
1181 spin_lock_irqsave(&pdev->lock, flags);
1182 pep->ep_state |= EP_WEDGE;
1184 spin_unlock_irqrestore(&pdev->lock, flags);
1215 struct cdnsp_device *pdev = pep->pdev;
1217 list_del(&preq->list);
1219 if (preq->request.status == -EINPROGRESS)
1220 preq->request.status = status;
1222 usb_gadget_unmap_request_by_dev(pdev->dev, &preq->request,
1223 preq->direction);
1227 if (preq != &pdev->ep0_preq) {
1228 spin_unlock(&pdev->lock);
1229 usb_gadget_giveback_request(&pep->endpoint, &preq->request);
1230 spin_lock(&pdev->lock);
1247 temp = readl(&pdev->ir_set->irq_control);
1250 writel(temp, &pdev->ir_set->irq_control);
1252 temp = readl(&pdev->port3x_regs->mode_addr);
1267 dev_err(pdev->dev, "invalid maximum_speed parameter %d\n",
1277 writel(temp, &pdev->port3x_regs->mode_addr);
1278 cdnsp_set_link_state(pdev, &pdev->usb3_port.regs->portsc,
1281 cdnsp_disable_port(pdev, &pdev->usb3_port.regs->portsc);
1284 cdnsp_set_link_state(pdev, &pdev->usb2_port.regs->portsc,
1289 writel(PORT_REG6_L1_L0_HW_EN | fs_speed, &pdev->port20_regs->port_reg6);
1293 ret = -ENODEV;
1297 temp = readl(&pdev->op_regs->command);
1299 writel(temp, &pdev->op_regs->command);
1301 temp = readl(&pdev->ir_set->irq_pending);
1302 writel(IMAN_IE_SET(temp), &pdev->ir_set->irq_pending);
1314 enum usb_device_speed max_speed = driver->max_speed;
1319 spin_lock_irqsave(&pdev->lock, flags);
1320 pdev->gadget_driver = driver;
1323 max_speed = min(driver->max_speed, g->max_speed);
1326 spin_unlock_irqrestore(&pdev->lock, flags);
1333 * - When all events have finished
1334 * - To avoid "Event Ring Full Error" condition
1343 temp_64 = cdnsp_read_64(&pdev->ir_set->erst_dequeue);
1346 if (event_ring_deq != pdev->event_ring->dequeue) {
1347 deq = cdnsp_trb_virt_to_dma(pdev->event_ring->deq_seg,
1348 pdev->event_ring->dequeue);
1359 cdnsp_write_64(temp_64, &pdev->ir_set->erst_dequeue);
1368 cdnsp_initialize_ring_info(pdev->cmd_ring);
1370 seg = pdev->cmd_ring->first_seg;
1371 for (i = 0; i < pdev->cmd_ring->num_segs; i++) {
1372 memset(seg->trbs, 0,
1373 sizeof(union cdnsp_trb) * (TRBS_PER_SEGMENT - 1));
1374 seg = seg->next;
1378 val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring);
1380 (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) |
1381 pdev->cmd_ring->cycle_state;
1382 cdnsp_write_64(val_64, &pdev->op_regs->cmd_ring);
1392 event_ring_deq = pdev->event_ring->dequeue;
1393 event_deq_seg = pdev->event_ring->deq_seg;
1394 event = pdev->event_ring->dequeue;
1398 cycle_bit = (le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE);
1401 if (cycle_bit != pdev->event_ring->cycle_state)
1404 cdnsp_inc_deq(pdev, pdev->event_ring);
1411 if (cdnsp_last_trb_on_ring(pdev->event_ring, event_deq_seg,
1415 event_deq_seg = event_deq_seg->next;
1416 event = event_deq_seg->trbs;
1427 if (!list_empty(&pdev->eps[0].pending_list)) {
1430 req = next_request(&pdev->eps[0].pending_list);
1431 if (req == &pdev->ep0_preq)
1432 cdnsp_ep_dequeue(&pdev->eps[0], req);
1435 cdnsp_disable_port(pdev, &pdev->usb2_port.regs->portsc);
1436 cdnsp_disable_port(pdev, &pdev->usb3_port.regs->portsc);
1440 temp = readl(&pdev->op_regs->status);
1441 writel((temp & ~0x1fff) | STS_EINT, &pdev->op_regs->status);
1442 temp = readl(&pdev->ir_set->irq_pending);
1443 writel(IMAN_IE_CLEAR(temp), &pdev->ir_set->irq_pending);
1445 cdnsp_clear_port_change_bit(pdev, &pdev->usb2_port.regs->portsc);
1446 cdnsp_clear_port_change_bit(pdev, &pdev->usb3_port.regs->portsc);
1449 temp = readl(&pdev->ir_set->irq_pending);
1451 writel(temp, &pdev->ir_set->irq_pending);
1469 spin_lock_irqsave(&pdev->lock, flags);
1471 pdev->gadget_driver = NULL;
1472 spin_unlock_irqrestore(&pdev->lock, flags);
1489 port_regs = pdev->active_port->regs;
1490 portsc = readl(&port_regs->portsc) & PORT_PLS_MASK;
1493 if (pdev->gadget.speed < USB_SPEED_SUPER && portsc == XDEV_U2) {
1494 portpm = readl(&port_regs->portpmsc);
1500 if (portsc == XDEV_U3 && !pdev->may_wakeup)
1503 cdnsp_set_link_state(pdev, &port_regs->portsc, XDEV_U0);
1505 pdev->cdnsp_state |= CDNSP_WAKEUP_PENDING;
1513 spin_lock_irqsave(&pdev->lock, flags);
1515 spin_unlock_irqrestore(&pdev->lock, flags);
1526 spin_lock_irqsave(&pdev->lock, flags);
1527 g->is_selfpowered = !!is_selfpowered;
1528 spin_unlock_irqrestore(&pdev->lock, flags);
1536 struct cdns *cdns = dev_get_drvdata(pdev->dev);
1545 disable_irq(cdns->dev_irq);
1546 spin_lock_irqsave(&pdev->lock, flags);
1555 spin_unlock_irqrestore(&pdev->lock, flags);
1556 enable_irq(cdns->dev_irq);
1573 void __iomem *reg = &pdev->cap_regs->hc_capbase;
1578 if (!pep->direction) {
1579 pep->buffering = readl(reg + XBUF_RX_TAG_MASK_0_OFFSET);
1580 pep->buffering_period = readl(reg + XBUF_RX_TAG_MASK_1_OFFSET);
1581 pep->buffering = (pep->buffering + 1) / 2;
1582 pep->buffering_period = (pep->buffering_period + 1) / 2;
1586 endpoints = HCS_ENDPOINTS(pdev->hcs_params1) / 2;
1590 /* Set reg to XBUF_TX_TAG_MASK_N related with this endpoint. */
1591 reg += pep->number * sizeof(u32) * 2;
1593 pep->buffering = (readl(reg) + 1) / 2;
1594 pep->buffering_period = pep->buffering;
1599 int max_streams = HCC_MAX_PSA(pdev->hcc_params);
1603 INIT_LIST_HEAD(&pdev->gadget.ep_list);
1606 dev_err(pdev->dev, "Stream size %d not supported\n",
1608 return -EINVAL;
1614 bool direction = !(i & 1); /* Start from OUT endpoint. */
1620 pep = &pdev->eps[i];
1621 pep->pdev = pdev;
1622 pep->number = epnum;
1623 pep->direction = direction; /* 0 for OUT, 1 for IN. */
1627 * pdev->eps[0]
1630 snprintf(pep->name, sizeof(pep->name), "ep%d%s",
1633 pep->idx = 0;
1634 usb_ep_set_maxpacket_limit(&pep->endpoint, 512);
1635 pep->endpoint.maxburst = 1;
1636 pep->endpoint.ops = &cdnsp_gadget_ep0_ops;
1637 pep->endpoint.desc = &cdnsp_gadget_ep0_desc;
1638 pep->endpoint.comp_desc = NULL;
1639 pep->endpoint.caps.type_control = true;
1640 pep->endpoint.caps.dir_in = true;
1641 pep->endpoint.caps.dir_out = true;
1643 pdev->ep0_preq.epnum = pep->number;
1644 pdev->ep0_preq.pep = pep;
1645 pdev->gadget.ep0 = &pep->endpoint;
1647 snprintf(pep->name, sizeof(pep->name), "ep%d%s",
1648 epnum, (pep->direction) ? "in" : "out");
1650 pep->idx = (epnum * 2 + (direction ? 1 : 0)) - 1;
1651 usb_ep_set_maxpacket_limit(&pep->endpoint, 1024);
1653 pep->endpoint.max_streams = max_streams;
1654 pep->endpoint.ops = &cdnsp_gadget_ep_ops;
1655 list_add_tail(&pep->endpoint.ep_list,
1656 &pdev->gadget.ep_list);
1658 pep->endpoint.caps.type_iso = true;
1659 pep->endpoint.caps.type_bulk = true;
1660 pep->endpoint.caps.type_int = true;
1662 pep->endpoint.caps.dir_in = direction;
1663 pep->endpoint.caps.dir_out = !direction;
1666 pep->endpoint.name = pep->name;
1667 pep->in_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, pep->idx);
1668 pep->out_ctx = cdnsp_get_ep_ctx(&pdev->out_ctx, pep->idx);
1671 dev_dbg(pdev->dev, "Init %s, MPS: %04x SupType: "
1674 pep->name, 1024,
1675 str_yes_no(pep->endpoint.caps.type_control),
1676 str_yes_no(pep->endpoint.caps.type_int),
1677 str_yes_no(pep->endpoint.caps.type_bulk),
1678 str_yes_no(pep->endpoint.caps.type_iso),
1679 str_yes_no(pep->endpoint.caps.dir_in),
1680 str_yes_no(pep->endpoint.caps.dir_out));
1682 INIT_LIST_HEAD(&pep->pending_list);
1694 pep = &pdev->eps[i];
1695 if (pep->number != 0 && pep->out_ctx)
1696 list_del(&pep->endpoint.ep_list);
1702 pdev->cdnsp_state |= CDNSP_STATE_DISCONNECT_PENDING;
1704 if (pdev->gadget_driver && pdev->gadget_driver->disconnect) {
1705 spin_unlock(&pdev->lock);
1706 pdev->gadget_driver->disconnect(&pdev->gadget);
1707 spin_lock(&pdev->lock);
1710 pdev->gadget.speed = USB_SPEED_UNKNOWN;
1711 usb_gadget_set_state(&pdev->gadget, USB_STATE_NOTATTACHED);
1713 pdev->cdnsp_state &= ~CDNSP_STATE_DISCONNECT_PENDING;
1718 if (pdev->gadget_driver && pdev->gadget_driver->suspend) {
1719 spin_unlock(&pdev->lock);
1720 pdev->gadget_driver->suspend(&pdev->gadget);
1721 spin_lock(&pdev->lock);
1727 if (pdev->gadget_driver && pdev->gadget_driver->resume) {
1728 spin_unlock(&pdev->lock);
1729 pdev->gadget_driver->resume(&pdev->gadget);
1730 spin_lock(&pdev->lock);
1740 port_regs = pdev->active_port->regs;
1741 pdev->gadget.speed = cdnsp_port_speed(readl(port_regs));
1743 spin_unlock(&pdev->lock);
1744 usb_gadget_udc_reset(&pdev->gadget, pdev->gadget_driver);
1745 spin_lock(&pdev->lock);
1747 switch (pdev->gadget.speed) {
1751 pdev->gadget.ep0->maxpacket = 512;
1756 pdev->gadget.ep0->maxpacket = 64;
1760 dev_err(pdev->dev, "Unknown device speed\n");
1766 usb_gadget_set_state(&pdev->gadget, USB_STATE_DEFAULT);
1771 void __iomem *reg = &pdev->cap_regs->hc_capbase;
1774 pdev->rev_cap = reg;
1776 dev_info(pdev->dev, "Rev: %08x/%08x, eps: %08x, buff: %08x/%08x\n",
1777 readl(&pdev->rev_cap->ctrl_revision),
1778 readl(&pdev->rev_cap->rtl_revision),
1779 readl(&pdev->rev_cap->ep_supported),
1780 readl(&pdev->rev_cap->rx_buff_size),
1781 readl(&pdev->rev_cap->tx_buff_size));
1789 pdev->cap_regs = pdev->regs;
1790 pdev->op_regs = pdev->regs +
1791 HC_LENGTH(readl(&pdev->cap_regs->hc_capbase));
1792 pdev->run_regs = pdev->regs +
1793 (readl(&pdev->cap_regs->run_regs_off) & RTSOFF_MASK);
1795 /* Cache read-only capability registers */
1796 pdev->hcs_params1 = readl(&pdev->cap_regs->hcs_params1);
1797 pdev->hcc_params = readl(&pdev->cap_regs->hc_capbase);
1798 pdev->hci_version = HC_VERSION(pdev->hcc_params);
1799 pdev->hcc_params = readl(&pdev->cap_regs->hcc_params);
1814 * Set dma_mask and coherent_dma_mask to 64-bits,
1815 * if controller supports 64-bit addressing.
1817 if (HCC_64BIT_ADDR(pdev->hcc_params) &&
1818 !dma_set_mask(pdev->dev, DMA_BIT_MASK(64))) {
1819 dev_dbg(pdev->dev, "Enabling 64-bit DMA addresses.\n");
1820 dma_set_coherent_mask(pdev->dev, DMA_BIT_MASK(64));
1823 * This is to avoid error in cases where a 32-bit USB
1824 * controller is used on a 64-bit capable system.
1826 ret = dma_set_mask(pdev->dev, DMA_BIT_MASK(32));
1830 dev_dbg(pdev->dev, "Enabling 32-bit DMA addresses.\n");
1831 dma_set_coherent_mask(pdev->dev, DMA_BIT_MASK(32));
1834 spin_lock_init(&pdev->lock);
1845 reg = readl(&pdev->port3x_regs->mode_2);
1847 writel(reg, &pdev->port3x_regs->mode_2);
1856 int ret = -ENOMEM;
1862 return -ENOMEM;
1864 pm_runtime_get_sync(cdns->dev);
1866 cdns->gadget_dev = pdev;
1867 pdev->dev = cdns->dev;
1868 pdev->regs = cdns->dev_regs;
1869 max_speed = usb_get_maximum_speed(cdns->dev);
1878 dev_err(cdns->dev, "invalid speed parameter %d\n", max_speed);
1886 pdev->gadget.ops = &cdnsp_gadget_ops;
1887 pdev->gadget.name = "cdnsp-gadget";
1888 pdev->gadget.speed = USB_SPEED_UNKNOWN;
1889 pdev->gadget.sg_supported = 1;
1890 pdev->gadget.max_speed = max_speed;
1891 pdev->gadget.lpm_capable = 1;
1893 pdev->setup_buf = kzalloc(CDNSP_EP0_SETUP_SIZE, GFP_KERNEL);
1894 if (!pdev->setup_buf)
1901 pdev->gadget.quirk_ep_out_aligned_size = true;
1905 dev_err(pdev->dev, "Generic initialization failed %d\n", ret);
1911 dev_err(pdev->dev, "failed to initialize endpoints\n");
1915 ret = usb_add_gadget_udc(pdev->dev, &pdev->gadget);
1917 dev_err(pdev->dev, "failed to register udc\n");
1921 ret = devm_request_threaded_irq(pdev->dev, cdns->dev_irq,
1924 dev_name(pdev->dev), pdev);
1931 usb_del_gadget_udc(&pdev->gadget);
1939 kfree(pdev->setup_buf);
1948 struct cdnsp_device *pdev = cdns->gadget_dev;
1950 devm_free_irq(pdev->dev, cdns->dev_irq, pdev);
1951 pm_runtime_mark_last_busy(cdns->dev);
1952 pm_runtime_put_autosuspend(cdns->dev);
1953 usb_del_gadget_udc(&pdev->gadget);
1957 cdns->gadget_dev = NULL;
1963 struct cdnsp_device *pdev = cdns->gadget_dev;
1966 if (pdev->link_state == XDEV_U3)
1969 spin_lock_irqsave(&pdev->lock, flags);
1972 spin_unlock_irqrestore(&pdev->lock, flags);
1979 struct cdnsp_device *pdev = cdns->gadget_dev;
1984 if (!pdev->gadget_driver)
1987 spin_lock_irqsave(&pdev->lock, flags);
1988 max_speed = pdev->gadget_driver->max_speed;
1991 max_speed = min(max_speed, pdev->gadget.max_speed);
1995 if (pdev->link_state == XDEV_U3)
1998 spin_unlock_irqrestore(&pdev->lock, flags);
2004 * cdnsp_gadget_init - initialize device structure
2013 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
2015 return -ENOMEM;
2017 rdrv->start = __cdnsp_gadget_init;
2018 rdrv->stop = cdnsp_gadget_exit;
2019 rdrv->suspend = cdnsp_gadget_suspend;
2020 rdrv->resume = cdnsp_gadget_resume;
2021 rdrv->state = CDNS_ROLE_STATE_INACTIVE;
2022 rdrv->name = "gadget";
2023 cdns->roles[USB_ROLE_DEVICE] = rdrv;