Lines Matching +full:axi +full:- +full:pcie +full:- +full:host +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
43 * @usb_cap1: Capability 1.
49 * @usb_cpkt1: Custom Packet 1.
53 * @buf_addr: Address for On-chip Buffer operations.
54 * @buf_data: Data for On-chip Buffer operations.
55 * @buf_ctrl: On-chip Buffer Access Control.
65 * @dma_axi_ctrl: AXI Control.
66 * @dma_axi_id: AXI ID register.
67 * @dma_axi_cap: AXI Capability.
68 * @dma_axi_ctrl0: AXI Control 0.
69 * @dma_axi_ctrl1: AXI Control 1.
123 /* USB_CONF - bitmasks */
127 #define USB_CONF_CFGSET BIT(1)
132 /* Little Endian access - default */
146 /* DMA clock turn-off enable. */
148 /* DMA clock turn-off disable. */
190 /* USB_STS - bitmasks */
193 * 1 - device is in the configured state.
194 * 0 - device is not configured.
199 * On-chip memory overflow.
200 * 0 - On-chip memory status OK.
201 * 1 - On-chip memory overflow.
203 #define USB_STS_OV_MASK BIT(1)
207 * 0 - USB in SuperSpeed mode disconnected.
208 * 1 - USB in SuperSpeed mode connected.
214 * 0 - single request.
215 * 1 - multiple TRB chain
222 * 0 - Undefined (value after reset).
223 * 1 - Low speed
224 * 2 - Full speed
225 * 3 - High speed
226 * 4 - Super speed
241 * 0 - Little Endian order (default after hardware reset).
242 * 1 - Big Endian order
247 * HS/FS clock turn-off status.
248 * 0 - hsfs clock is always on.
249 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
255 * PCLK clock turn-off status.
256 * 0 - pclk clock is always on.
257 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
264 * 0 - Internal reset is active.
265 * 1 - Internal reset is not active and controller is fully operational.
271 * 0 - disabled
272 * 1 - enabled
278 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
279 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
285 * 0 - USB device is default state.
286 * 1 - USB device is at least in address state.
292 * 0 - Entering to L1 LPM state disabled.
293 * 1 - Entering to L1 LPM state enabled.
299 * 0 - internal VBUS is not detected.
300 * 1 - internal VBUS is detected.
306 * 0 - L0 State
307 * 1 - L1 State
308 * 2 - L2 State
309 * 3 - L3 State
318 * 0 - the disconnect bit for HS/FS mode is set .
319 * 1 - the disconnect bit for HS/FS mode is not set.
325 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
326 * 1 - High Speed operations in USB2.0 (FS/HS).
332 * 0 - Entering to U1 state disabled.
333 * 1 - Entering to U1 state enabled.
339 * 0 - Entering to U2 state disabled.
340 * 1 - Entering to U2 state enabled.
345 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
362 * DMA clock turn-off status.
363 * 0 - DMA clock is always on (default after hardware reset).
364 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
370 * 0 - Little Endian order (default after hardware reset).
371 * 1 - Big Endian order.
376 /* USB_CMD - bitmasks */
381 * SET_ADDR is set '1 ' during write to USB_CMD register.
386 #define USB_CMD_FADDR_MASK GENMASK(7, 1)
387 #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
402 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
406 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
412 /* USB_ITPN - bitmasks */
415 * In SS mode this field represent number of last ITP received from host.
416 * In HS/FS mode this field represent number of last SOF received from host.
421 /* USB_LPM - bitmasks */
422 /* Host Initiated Resume Duration. */
428 /* USB_IEN - bitmasks */
432 #define USB_IEN_DISIEN BIT(1)
481 /* USB_ISTS - bitmasks */
485 #define USB_ISTS_DISI BIT(1)
529 /* USB_SEL - bitmasks */
533 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
539 /* EP_TRADDR - bitmasks */
543 /* EP_CFG - bitmasks */
548 * 1 - isochronous
549 * 2 - bulk
550 * 3 - interrupt
552 #define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
553 #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
578 /* EP_CMD - bitmasks */
582 #define EP_CMD_SSTALL BIT(1)
612 /* EP_STS - bitmasks */
616 #define EP_STS_STALL(p) ((p) & BIT(1))
645 /* Host Packet Pending (only for SS mode). */
664 /* EP_STS_SID - bitmasks */
669 /* EP_STS_EN - bitmasks */
695 /* DRBL- bitmasks */
696 #define DB_VALUE_BY_INDEX(index) (1 << (index))
700 /* EP_IEN - bitmasks */
701 #define EP_IEN(index) (1 << (index))
705 /* EP_ISTS - bitmasks */
706 #define EP_ISTS(index) (1 << (index))
710 /* USB_PWR- bitmasks */
714 #define PUSB_PWR_PSO_DS BIT(1)
716 * Enables turning-off Reference Clock.
718 * implemented (indicated by OTG_READY bit set to '1').
731 /* USB_CONF2- bitmasks */
733 * Writing 1 disables TDL calculation basing on TRB feature in controller
737 #define USB_CONF2_DIS_TDL_TRB BIT(1)
739 * Writing 1 enables TDL calculation basing on TRB feature in controller
745 /* USB_CAP1- bitmasks */
749 * 0x0 - OCP
750 * 0x1 - AHB,
751 * 0x2 - PLB
752 * 0x3 - AXI
753 * 0x4-0xF - reserved
763 * 0x0 - 8 bit interface,
764 * 0x1 - 16 bit interface,
765 * 0x2 - 32 bit interface
766 * 0x3 - 64 bit interface
767 * 0x4-0xF - reserved
777 * 0x0 - OCP
778 * 0x1 - AHB,
779 * 0x2 - PLB
780 * 0x3 - AXI
781 * 0x4-0xF - reserved
791 * 0x0 - reserved,
792 * 0x1 - reserved,
793 * 0x2 - 32 bit interface
794 * 0x3 - 64 bit interface
795 * 0x4-0xF - reserved
803 * 0x0 - USB PIPE,
804 * 0x1 - RMMI,
805 * 0x2-0xF - reserved
813 * 0x0 - 8 bit PIPE interface,
814 * 0x1 - 16 bit PIPE interface,
815 * 0x2 - 32 bit PIPE interface,
816 * 0x3 - 64 bit PIPE interface
817 * 0x4-0xF - reserved
834 * 0x0 - interface NOT implemented,
835 * 0x1 - interface implemented
841 * 0x0 - UTMI,
842 * 0x1 - ULPI
848 * 0x0 - 8 bit interface,
849 * 0x1 - 16 bit interface,
855 * 0x0 - pure device mode
856 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
867 /* USB_CAP2- bitmasks */
869 * The actual size of the connected On-chip RAM memory in kB:
870 * - 0 means 256 kB (max supported mem size)
871 * - value other than 0 reflects the mem size in kB
876 * These field reflects width of on-chip RAM address bus width,
878 * 0x0-0x7 - reserved,
879 * 0x8 - support for 4kB mem,
880 * 0x9 - support for 8kB mem,
881 * 0xA - support for 16kB mem,
882 * 0xB - support for 32kB mem,
883 * 0xC - support for 64kB mem,
884 * 0xD - support for 128kB mem,
885 * 0xE - support for 256kB mem,
886 * 0xF - reserved
890 /* USB_CAP3- bitmasks */
891 #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
893 /* USB_CAP4- bitmasks */
894 #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
896 /* USB_CAP5- bitmasks */
897 #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
899 /* USB_CAP6- bitmasks */
900 /* The USBSS-DEV Controller Internal build number. */
902 /* The USBSS-DEV Controller version number. */
910 /* DBG_LINK1- bitmasks */
923 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
927 * 1: USBSS_DEV will not terminate Far-end receiver termination
934 * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
940 * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
946 * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
952 * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
958 /* DMA_AXI_CTRL- bitmasks */
969 /*-------------------------------------------------------------------------*/
971 * USBSS-DEV DMA interface.
990 *Only for ISOC endpoints - maximum number of TRBs is calculated as
991 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
993 * if bInterval > 1. It's the reason why driver needs so many TRBs for
1001 * struct cdns3_trb - represent Transfer Descriptor block.
1027 #define TRB_NORMAL 1
1031 /* Cycle bit - indicates TRB ownership by driver or hw*/
1034 * When set to '1', the device will toggle its interpretation of the Cycle bit
1036 #define TRB_TOGGLE BIT(1)
1041 #define TRB_SMM BIT(1)
1044 * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1047 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1048 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1051 #define TRB_SP BIT(1)
1057 /* Set PCIe no snoop attribute */
1078 /* transfer_len bitmasks - bits 31:24 */
1085 /*-------------------------------------------------------------------------*/
1103 /*-------------------------------------------------------------------------*/
1109 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1114 * @trb_pool: transfer ring - array of transaction buffers
1119 * @descmis_req: internal transfer object used for getting data from on-chip
1123 * @num: endpoint number (1 - 15)
1149 #define EP_STALLED BIT(1)
1185 unsigned int wa1_set:1;
1188 unsigned int wa1_cycle_bit:1;
1191 unsigned int use_streams:1;
1192 unsigned int prime_flag:1;
1200 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1213 unsigned in_use:1;
1218 * struct cdns3_request - extended device side representation of usb_request
1240 #define REQUEST_INTERNAL BIT(1)
1258 * struct cdns3_device - represent USB device.
1268 * @zlp_buf - zlp buffer
1282 * @wake_up_flag: allow device to remote up the host
1285 * @onchip_buffers: number of available on-chip buffers.
1286 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1301 /* generic spin-lock for drivers */
1322 unsigned wait_for_setup:1;
1323 unsigned u1_allowed:1;
1324 unsigned u2_allowed:1;
1325 unsigned is_selfpowered:1;
1326 unsigned setup_pending:1;
1327 unsigned hw_configured_flag:1;
1328 unsigned wake_up_flag:1;
1329 unsigned status_completion_no_call:1;
1330 unsigned using_streams:1;