Lines Matching +full:ufs +full:- +full:2

1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 #include <linux/reset-controller.h>
11 #include <ufs/ufshcd.h>
27 /* QCOM UFS host controller vendor specific registers */
33 	/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
35 	/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
48 	 * QCOM UFS host controller vendor specific registers
63 /* QCOM UFS host controller vendor specific debug registers */
80 /* QCOM UFS HC vendor specific Hibern8 count registers */
110 #define TXUC_HW_CGC_EN		BIT(2)
127 /* bit definition for UFS Shared ICE config */
149 /* QCOM UFS host controller core clk frequencies */
162  * Some ufs device vendors need a different TSync length.
168  * Some ufs device vendors need a different Deemphasis setting.
174 #define ICE_ALLOCATOR_TYPE 2
197  * Number of cores allocated for TX stream (UFS write) when Read data block
294 	if (host->hw_ver.major <= 0x02)  in ufs_qcom_get_debug_reg_offset()