Lines Matching +full:0 +full:x1900
13 #define MPHY_TX_FSM_STATE 0x41
14 #define TX_FSM_HIBERN8 0x1
22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
28 #define PA_VS_CLK_CFG_REG 0x9004
29 #define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0)
32 #define DL_VS_CLK_CFG 0xA00B
33 #define DL_VS_CLK_CFG_MASK GENMASK(9, 0)
38 REG_UFS_SYS1CLK_1US = 0xC0,
39 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
40 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
41 REG_UFS_PA_ERR_CODE = 0xCC,
43 REG_UFS_PARAM0 = 0xD0,
45 REG_UFS_CFG0 = 0xD8,
46 REG_UFS_CFG1 = 0xDC,
47 REG_UFS_CFG2 = 0xE0,
48 REG_UFS_HW_VERSION = 0xE4,
50 UFS_TEST_BUS = 0xE8,
51 UFS_TEST_BUS_CTRL_0 = 0xEC,
52 UFS_TEST_BUS_CTRL_1 = 0xF0,
53 UFS_TEST_BUS_CTRL_2 = 0xF4,
54 UFS_UNIPRO_CFG = 0xF8,
58 * added in HW Version 3.0.0
60 UFS_AH8_CFG = 0xFC,
62 UFS_RD_REG_MCQ = 0xD00,
64 REG_UFS_MEM_ICE_CONFIG = 0x260C,
65 REG_UFS_MEM_ICE_NUM_CORE = 0x2664,
67 REG_UFS_CFG3 = 0x271C,
69 REG_UFS_DEBUG_SPARE_CFG = 0x284C,
74 UFS_DBG_RD_REG_UAWM = 0x100,
75 UFS_DBG_RD_REG_UARM = 0x200,
76 UFS_DBG_RD_REG_TXUC = 0x300,
77 UFS_DBG_RD_REG_RXUC = 0x400,
78 UFS_DBG_RD_REG_DFC = 0x500,
79 UFS_DBG_RD_REG_TRLUT = 0x600,
80 UFS_DBG_RD_REG_TMRLUT = 0x700,
81 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
83 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
84 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
85 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
86 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
91 REG_UFS_HW_H8_ENTER_CNT = 0x2700,
92 REG_UFS_SW_H8_ENTER_CNT = 0x2704,
93 REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708,
94 REG_UFS_HW_H8_EXIT_CNT = 0x270C,
95 REG_UFS_SW_H8_EXIT_CNT = 0x2710,
99 UFS_MEM_CQIS_VS = 0x8,
102 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
103 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
109 #define QUNIPRO_SEL BIT(0)
117 #define UAWM_HW_CGC_EN BIT(0)
134 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
137 #define UFS_QCOM_CAP_ICE_CONFIG BIT(0)
145 #define PA_TX_HSG1_SYNC_LENGTH 0x1552
146 #define PA_VS_CONFIG_REG1 0x9000
147 #define DME_VS_CORE_CLK_CTRL 0xD002
148 #define TX_HS_EQUALIZER 0x0037
152 #define CLK_1US_CYCLES_MASK GENMASK(7, 0)
154 #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007
155 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0)
168 #define PA_TX_HSG1_SYNC_LENGTH_VAL 0x4A
237 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);
303 if (host->hw_ver.major <= 0x02)
312 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1))