Lines Matching +full:hw +full:- +full:settle +full:- +full:time +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
27 #include "ufshcd-pltfrm.h"
28 #include "ufs-qcom.h"
36 /* De-emphasis for gear-5 */
115 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration
121 struct ufs_hba *hba = host->hba; in ufs_qcom_config_ice_allocator()
125 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || in ufs_qcom_config_ice_allocator()
126 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) in ufs_qcom_config_ice_allocator()
137 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
138 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
145 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
146 struct blk_crypto_profile *profile = &hba->crypto_profile; in ufs_qcom_ice_init()
147 struct device *dev = hba->dev; in ufs_qcom_ice_init()
155 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
163 host->ice = ice; in ufs_qcom_ice_init()
174 profile->ll_ops = ufs_qcom_crypto_ops; in ufs_qcom_ice_init()
175 profile->max_dun_bytes_supported = 8; in ufs_qcom_ice_init()
176 profile->key_types_supported = BLK_CRYPTO_KEY_TYPE_RAW; in ufs_qcom_ice_init()
177 profile->dev = dev; in ufs_qcom_ice_init()
180 * Currently this driver only supports AES-256-XTS. All known versions in ufs_qcom_ice_init()
191 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= in ufs_qcom_ice_init()
195 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
196 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; in ufs_qcom_ice_init()
202 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
203 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
210 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
211 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
224 /* Only AES-256-XTS has been tested so far. */ in ufs_qcom_ice_keyslot_program()
225 if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS) in ufs_qcom_ice_keyslot_program()
226 return -EOPNOTSUPP; in ufs_qcom_ice_keyslot_program()
229 err = qcom_ice_program_key(host->ice, in ufs_qcom_ice_keyslot_program()
232 key->bytes, in ufs_qcom_ice_keyslot_program()
233 key->crypto_cfg.data_unit_size / 512, in ufs_qcom_ice_keyslot_program()
248 err = qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_keyslot_evict()
287 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
290 clk_bulk_disable_unprepare(host->num_clks, host->clks); in ufs_qcom_disable_lane_clks()
292 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
299 err = clk_bulk_prepare_enable(host->num_clks, host->clks); in ufs_qcom_enable_lane_clks()
303 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
311 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
316 err = devm_clk_bulk_get_all(dev, &host->clks); in ufs_qcom_init_lane_clks()
320 host->num_clks = err; in ufs_qcom_init_lane_clks()
339 /* sleep for max. 200us */ in ufs_qcom_check_hibern8()
354 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
358 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
367 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
369 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
370 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
374 * ufs_qcom_host_reset - reset host controller and PHY
382 if (!host->core_reset) in ufs_qcom_host_reset()
385 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
388 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
390 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
397 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
398 * ~125us (4/32768). To be on the safe side add 200us delay. in ufs_qcom_host_reset()
402 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
404 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
421 if (host->hw_ver.major >= 0x4) in ufs_qcom_get_hs_gear()
424 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
431 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_power_up_sequence()
432 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
437 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. in ufs_qcom_power_up_sequence()
438 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, in ufs_qcom_power_up_sequence()
439 * so that the subsequent power mode change shall stick to Rate-A. in ufs_qcom_power_up_sequence()
441 if (host->hw_ver.major == 0x5) { in ufs_qcom_power_up_sequence()
442 if (host->phy_gear == UFS_HS_G5) in ufs_qcom_power_up_sequence()
443 host_params->hs_rate = PA_HS_MODE_A; in ufs_qcom_power_up_sequence()
445 host_params->hs_rate = PA_HS_MODE_B; in ufs_qcom_power_up_sequence()
448 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; in ufs_qcom_power_up_sequence()
455 if (phy->power_count) { in ufs_qcom_power_up_sequence()
460 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
463 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
468 ret = phy_set_mode_ext(phy, mode, host->phy_gear); in ufs_qcom_power_up_sequence()
472 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
475 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
492 * Internal hardware sub-modules within the UTP controller control the CGCs.
493 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
503 /* Ensure that HW clock gating is enabled before next operations */ in ufs_qcom_enable_hw_clk_gating()
534 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
535 err = -EINVAL; in ufs_qcom_hce_enable_notify()
542 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
546 * Return: zero for success and non-zero in case of a failure.
561 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) in ufs_qcom_cfg_timers()
564 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
565 if (!strcmp(clki->name, "core_clk")) { in ufs_qcom_cfg_timers()
567 core_clk_rate = clki->max_freq; in ufs_qcom_cfg_timers()
569 core_clk_rate = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
600 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
602 return -EINVAL; in ufs_qcom_link_startup_notify()
607 dev_err(hba->dev, "cfg core clk ctrl failed\n"); in ufs_qcom_link_startup_notify()
630 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
633 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
640 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
667 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
673 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
693 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
694 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
695 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
698 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
700 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
705 * sure that device ref_clk is active for specific time after in ufs_qcom_dev_ref_clk_ctrl()
711 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
717 * time for which the reference clock is in ufs_qcom_dev_ref_clk_ctrl()
719 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
727 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
733 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
737 * device ref_clk is stable for at least 1us before the hibern8 in ufs_qcom_dev_ref_clk_ctrl()
743 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
749 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
752 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
758 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
769 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
770 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
771 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
784 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
814 dev_err(hba->dev, "%s: failed equalizer lane %d\n", in ufs_qcom_set_tx_hs_equalizer()
825 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_pwr_change_notify()
830 return -EINVAL; in ufs_qcom_pwr_change_notify()
837 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
848 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { in ufs_qcom_pwr_change_notify()
854 if (host->phy_gear == dev_req_params->gear_tx) in ufs_qcom_pwr_change_notify()
855 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_pwr_change_notify()
857 host->phy_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
861 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
865 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
867 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
871 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) in ufs_qcom_pwr_change_notify()
873 dev_req_params->gear_tx, dev_req_params->lane_tx); in ufs_qcom_pwr_change_notify()
878 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
885 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
889 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
895 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
900 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
929 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); in ufs_qcom_override_pa_tx_hsg1_sync_len()
936 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
939 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) in ufs_qcom_apply_dev_quirks()
945 /* UFS device-specific quirks */
974 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
984 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_advertise_quirks()
987 if (host->hw_ver.major == 0x2) in ufs_qcom_advertise_quirks()
988 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
990 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
991 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
993 if (drvdata && drvdata->quirks) in ufs_qcom_advertise_quirks()
994 hba->quirks |= drvdata->quirks; in ufs_qcom_advertise_quirks()
999 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_phy_gear()
1009 host->phy_gear = host_params->hs_tx_gear; in ufs_qcom_set_phy_gear()
1011 if (host->hw_ver.major < 0x4) { in ufs_qcom_set_phy_gear()
1017 host->phy_gear = UFS_HS_G2; in ufs_qcom_set_phy_gear()
1018 } else if (host->hw_ver.major >= 0x5) { in ufs_qcom_set_phy_gear()
1019 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
1028 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_set_phy_gear()
1031 * For UFS 3.1 device and older, power up the PHY using HS-G4 in ufs_qcom_set_phy_gear()
1035 host->phy_gear = UFS_HS_G4; in ufs_qcom_set_phy_gear()
1042 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_host_params()
1047 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); in ufs_qcom_set_host_params()
1054 if (host->hw_ver.major >= 0x5) in ufs_qcom_set_host_caps()
1055 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; in ufs_qcom_set_host_caps()
1060 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
1061 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
1062 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
1063 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
1064 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
1065 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
1071 * ufs_qcom_setup_clocks - enables/disable clocks
1076 * Return: 0 on success, non-zero on failure.
1105 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
1122 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
1133 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1137 * voltage, current to settle down before starting serdes. in ufs_qcom_reset_deassert()
1150 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1153 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
1154 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
1155 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
1158 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
1159 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
1160 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1177 * ufs_qcom_init - bind phy with controller
1183 * Return: -EPROBE_DEFER if binding fails, returns negative error
1189 struct device *dev = hba->dev; in ufs_qcom_init()
1192 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_init()
1196 return -ENOMEM; in ufs_qcom_init()
1199 host->hba = hba; in ufs_qcom_init()
1203 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1204 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1205 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1210 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1211 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1212 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1213 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1214 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1215 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1220 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1221 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1222 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1231 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1233 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1234 err = dev_err_probe(dev, PTR_ERR(host->device_reset), in ufs_qcom_init()
1239 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1240 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1242 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1243 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1245 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1246 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1247 clki->keep_link_active = true; in ufs_qcom_init()
1268 /* Failure is non-fatal */ in ufs_qcom_init()
1272 if (drvdata && drvdata->no_phy_retention) in ufs_qcom_init()
1273 hba->spm_lvl = UFS_PM_LVL_5; in ufs_qcom_init()
1288 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1289 phy_exit(host->generic_phy); in ufs_qcom_exit()
1293 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1296 * @cycles_in_1us: No of cycles in 1us to be configured
1314 if (host->hw_ver.major < 4) in ufs_qcom_set_clk_40ns_cycles()
1348 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", in ufs_qcom_set_clk_40ns_cycles()
1350 return -EINVAL; in ufs_qcom_set_clk_40ns_cycles()
1366 struct list_head *head = &hba->clk_list_head; in ufs_qcom_set_core_clk_ctrl()
1373 if (!IS_ERR_OR_NULL(clki->clk) && in ufs_qcom_set_core_clk_ctrl()
1374 !strcmp(clki->name, "core_clk_unipro")) { in ufs_qcom_set_core_clk_ctrl()
1375 if (!clki->max_freq) in ufs_qcom_set_core_clk_ctrl()
1378 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1393 if (host->hw_ver.major >= 4) { in ufs_qcom_set_core_clk_ctrl()
1395 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1400 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1424 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); in ufs_qcom_clk_scale_up_pre_change()
1508 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1510 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1516 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1517 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1522 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1523 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1525 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1539 return -EINVAL; in ufs_qcom_testbus_config()
1542 return -EPERM; in ufs_qcom_testbus_config()
1544 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1601 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1602 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1604 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1605 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1638 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1664 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1665 * @hba: per-adapter instance
1674 if (!host->device_reset) in ufs_qcom_device_reset()
1675 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1678 * The UFS device shall detect reset pulses of 1us, sleep for 10us to in ufs_qcom_device_reset()
1695 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1696 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1697 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1698 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1700 hba->clk_scaling.suspend_on_no_request = true; in ufs_qcom_config_scaling_param()
1728 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1733 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1736 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1737 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1739 res->name); in ufs_qcom_mcq_config_resource()
1740 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1741 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1743 return -ENODEV; in ufs_qcom_mcq_config_resource()
1746 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1747 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1751 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1752 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1753 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1754 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1755 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1756 res->base = NULL; in ufs_qcom_mcq_config_resource()
1762 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1764 if (res->base) in ufs_qcom_mcq_config_resource()
1768 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1770 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1772 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1773 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1774 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1775 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1776 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1780 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1785 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1786 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1787 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1788 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1789 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1794 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1797 res->base = NULL; in ufs_qcom_mcq_config_resource()
1808 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1809 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1811 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1812 return -EINVAL; in ufs_qcom_op_runtime_config()
1815 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1816 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
1817 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
1818 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
1819 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
1834 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1836 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
1837 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
1839 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
1857 u32 id = desc->msi_index; in ufs_qcom_mcq_esi_handler()
1858 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1873 if (host->esi_enabled) in ufs_qcom_config_esi()
1880 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1881 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1884 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1888 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1889 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1890 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1892 IRQF_SHARED, "qcom-mcq-esi", desc); in ufs_qcom_config_esi()
1894 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1895 __func__, desc->irq, ret); in ufs_qcom_config_esi()
1900 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1904 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1905 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1908 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1910 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1911 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_config_esi()
1913 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in ufs_qcom_config_esi()
1914 host->hw_ver.step == 0) in ufs_qcom_config_esi()
1916 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), in ufs_qcom_config_esi()
1919 host->esi_enabled = true; in ufs_qcom_config_esi()
1948 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); in ufs_qcom_freq_to_gear_speed()
1956 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1987 * ufs_qcom_probe - probe routine of the driver
1990 * Return: zero for success and non-zero for failure.
1995 struct device *dev = &pdev->dev; in ufs_qcom_probe()
2006 * ufs_qcom_remove - set driver_data of the device to NULL
2017 if (host->esi_enabled) in ufs_qcom_remove()
2018 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_remove()
2028 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2029 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2059 .name = "ufshcd-qcom",