Lines Matching +full:cpu +full:- +full:ufs
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
17 #include <linux/reset-controller.h>
24 #include <ufs/ufshcd.h>
25 #include <ufs/ufshci.h>
26 #include <ufs/ufs_quirks.h>
27 #include <ufs/unipro.h>
28 #include "ufshcd-pltfrm.h"
29 #include "ufs-qcom.h"
37 /* De-emphasis for gear-5 */
136 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration
142 struct ufs_hba *hba = host->hba; in ufs_qcom_config_ice_allocator()
146 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || in ufs_qcom_config_ice_allocator()
147 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) in ufs_qcom_config_ice_allocator()
158 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
159 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
166 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
167 struct blk_crypto_profile *profile = &hba->crypto_profile; in ufs_qcom_ice_init()
168 struct device *dev = hba->dev; in ufs_qcom_ice_init()
176 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
184 host->ice = ice; in ufs_qcom_ice_init()
195 profile->ll_ops = ufs_qcom_crypto_ops; in ufs_qcom_ice_init()
196 profile->max_dun_bytes_supported = 8; in ufs_qcom_ice_init()
197 profile->key_types_supported = qcom_ice_get_supported_key_type(ice); in ufs_qcom_ice_init()
198 profile->dev = dev; in ufs_qcom_ice_init()
201 * Currently this driver only supports AES-256-XTS. All known versions in ufs_qcom_ice_init()
212 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= in ufs_qcom_ice_init()
216 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
217 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; in ufs_qcom_ice_init()
223 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
224 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
231 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
232 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
246 err = qcom_ice_program_key(host->ice, slot, key); in ufs_qcom_ice_keyslot_program()
260 err = qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_keyslot_evict()
272 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size, in ufs_qcom_ice_derive_sw_secret()
283 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key); in ufs_qcom_ice_import_key()
292 return qcom_ice_generate_key(host->ice, lt_key); in ufs_qcom_ice_generate_key()
302 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); in ufs_qcom_ice_prepare_key()
343 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
346 clk_bulk_disable_unprepare(host->num_clks, host->clks); in ufs_qcom_disable_lane_clks()
348 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
355 err = clk_bulk_prepare_enable(host->num_clks, host->clks); in ufs_qcom_enable_lane_clks()
359 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
367 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
372 err = devm_clk_bulk_get_all(dev, &host->clks); in ufs_qcom_init_lane_clks()
376 host->num_clks = err; in ufs_qcom_init_lane_clks()
410 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
414 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
423 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
425 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
426 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
430 * ufs_qcom_host_reset - reset host controller and PHY
438 if (!host->core_reset) in ufs_qcom_host_reset()
441 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
444 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
446 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
453 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
458 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
460 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
477 if (host->hw_ver.major >= 0x4) in ufs_qcom_get_hs_gear()
480 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
487 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_power_up_sequence()
488 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
493 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. in ufs_qcom_power_up_sequence()
494 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, in ufs_qcom_power_up_sequence()
495 * so that the subsequent power mode change shall stick to Rate-A. in ufs_qcom_power_up_sequence()
497 if (host->hw_ver.major == 0x5) { in ufs_qcom_power_up_sequence()
498 if (host->phy_gear == UFS_HS_G5) in ufs_qcom_power_up_sequence()
499 host_params->hs_rate = PA_HS_MODE_A; in ufs_qcom_power_up_sequence()
501 host_params->hs_rate = PA_HS_MODE_B; in ufs_qcom_power_up_sequence()
504 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; in ufs_qcom_power_up_sequence()
506 /* Reset UFS Host Controller and PHY */ in ufs_qcom_power_up_sequence()
511 if (phy->power_count) in ufs_qcom_power_up_sequence()
515 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
518 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
523 ret = phy_set_mode_ext(phy, mode, host->phy_gear); in ufs_qcom_power_up_sequence()
527 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
530 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
547 * Internal hardware sub-modules within the UTP controller control the CGCs.
548 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
550 * this function enables them (after every UFS link startup) to save some power
582 /* check if UFS PHY moved from DISABLED to HIBERN8 */ in ufs_qcom_hce_enable_notify()
589 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
590 err = -EINVAL; in ufs_qcom_hce_enable_notify()
597 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
602 * Return: zero for success and non-zero in case of a failure.
614 * It is mandatory to write SYS1CLK_1US_REG register on UFS host in ufs_qcom_cfg_timers()
617 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) in ufs_qcom_cfg_timers()
620 if (hba->use_pm_opp && freq != ULONG_MAX) { in ufs_qcom_cfg_timers()
626 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
627 if (!strcmp(clki->name, "core_clk")) { in ufs_qcom_cfg_timers()
629 clk_freq = clki->max_freq; in ufs_qcom_cfg_timers()
634 clk_freq = clki->max_freq; in ufs_qcom_cfg_timers()
636 clk_freq = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
668 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
670 return -EINVAL; in ufs_qcom_link_startup_notify()
675 dev_err(hba->dev, "cfg core clk ctrl failed\n"); in ufs_qcom_link_startup_notify()
677 * Some UFS devices (and may be host) have issues if LCC is in ufs_qcom_link_startup_notify()
698 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
701 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
708 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
722 /* reset the connected UFS device during power down */ in ufs_qcom_suspend()
735 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
741 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
761 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
762 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
763 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
766 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
768 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
779 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
787 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
795 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
801 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
811 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
817 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
820 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
826 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
837 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
838 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
839 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
842 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", in ufs_qcom_get_bw_table()
847 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", in ufs_qcom_get_bw_table()
852 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
882 dev_err(hba->dev, "%s: failed equalizer lane %d\n", in ufs_qcom_set_tx_hs_equalizer()
893 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_pwr_change_notify()
898 return -EINVAL; in ufs_qcom_pwr_change_notify()
905 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
911 * During UFS driver probe, always update the PHY gear to match the negotiated in ufs_qcom_pwr_change_notify()
916 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { in ufs_qcom_pwr_change_notify()
922 if (host->phy_gear == dev_req_params->gear_tx) in ufs_qcom_pwr_change_notify()
923 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_pwr_change_notify()
925 host->phy_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
929 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
933 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
935 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
939 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) in ufs_qcom_pwr_change_notify()
941 dev_req_params->gear_tx, dev_req_params->lane_tx); in ufs_qcom_pwr_change_notify()
946 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
952 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
957 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
986 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); in ufs_qcom_override_pa_tx_hsg1_sync_len()
993 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
996 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) in ufs_qcom_apply_dev_quirks()
1002 /* UFS device-specific quirks */
1031 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1034 * QCOM UFS host controller might have some non standard behaviours (quirks)
1036 * quirks to standard UFS host controller driver so standard takes them into
1041 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_advertise_quirks()
1044 if (host->hw_ver.major == 0x2) in ufs_qcom_advertise_quirks()
1045 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
1047 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
1048 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
1050 if (drvdata && drvdata->quirks) in ufs_qcom_advertise_quirks()
1051 hba->quirks |= drvdata->quirks; in ufs_qcom_advertise_quirks()
1056 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_phy_gear()
1066 host->phy_gear = host_params->hs_tx_gear; in ufs_qcom_set_phy_gear()
1068 if (host->hw_ver.major < 0x4) { in ufs_qcom_set_phy_gear()
1074 host->phy_gear = UFS_HS_G2; in ufs_qcom_set_phy_gear()
1075 } else if (host->hw_ver.major >= 0x5) { in ufs_qcom_set_phy_gear()
1076 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
1080 * Since the UFS device version is populated, let's remove the in ufs_qcom_set_phy_gear()
1085 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_set_phy_gear()
1088 * For UFS 3.1 device and older, power up the PHY using HS-G4 in ufs_qcom_set_phy_gear()
1092 host->phy_gear = UFS_HS_G4; in ufs_qcom_set_phy_gear()
1099 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_host_params()
1104 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); in ufs_qcom_set_host_params()
1111 if (host->hw_ver.major >= 0x5) in ufs_qcom_set_host_caps()
1112 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; in ufs_qcom_set_host_caps()
1117 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
1118 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
1119 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
1120 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
1121 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
1122 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
1128 * ufs_qcom_setup_clocks - enables/disable clocks
1133 * Return: 0 on success, non-zero on failure.
1162 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
1179 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
1190 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1207 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1210 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
1211 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
1212 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
1215 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
1216 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
1217 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1221 * Set Maximum bandwidth vote before initializing the UFS controller and in ufs_qcom_icc_init()
1234 * ufs_qcom_init - bind phy with controller
1240 * Return: -EPROBE_DEFER if binding fails, returns negative error
1246 struct device *dev = hba->dev; in ufs_qcom_init()
1249 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_init()
1253 return -ENOMEM; in ufs_qcom_init()
1256 host->hba = hba; in ufs_qcom_init()
1260 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1261 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1262 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1267 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1268 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1269 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1270 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1271 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1272 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1277 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1278 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1279 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1288 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1290 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1291 err = dev_err_probe(dev, PTR_ERR(host->device_reset), in ufs_qcom_init()
1296 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1297 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1299 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1300 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1302 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1303 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1304 clki->keep_link_active = true; in ufs_qcom_init()
1325 /* Failure is non-fatal */ in ufs_qcom_init()
1329 if (drvdata && drvdata->no_phy_retention) in ufs_qcom_init()
1330 hba->spm_lvl = UFS_PM_LVL_5; in ufs_qcom_init()
1345 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1346 phy_exit(host->generic_phy); in ufs_qcom_exit()
1350 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1367 * UFS host controller V4.0.0 onwards needs to program in ufs_qcom_set_clk_40ns_cycles()
1369 * frequency of unipro core clk of UFS host controller. in ufs_qcom_set_clk_40ns_cycles()
1371 if (host->hw_ver.major < 4) in ufs_qcom_set_clk_40ns_cycles()
1405 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", in ufs_qcom_set_clk_40ns_cycles()
1407 return -EINVAL; in ufs_qcom_set_clk_40ns_cycles()
1423 struct list_head *head = &hba->clk_list_head; in ufs_qcom_set_core_clk_ctrl()
1430 if (hba->use_pm_opp && freq != ULONG_MAX) { in ufs_qcom_set_core_clk_ctrl()
1439 if (!IS_ERR_OR_NULL(clki->clk) && in ufs_qcom_set_core_clk_ctrl()
1440 !strcmp(clki->name, "core_clk_unipro")) { in ufs_qcom_set_core_clk_ctrl()
1441 if (!clki->max_freq) { in ufs_qcom_set_core_clk_ctrl()
1447 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1452 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1454 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1466 /* Bit mask is different for UFS host controller V4.0.0 onwards */ in ufs_qcom_set_core_clk_ctrl()
1467 if (host->hw_ver.major >= 4) { in ufs_qcom_set_core_clk_ctrl()
1469 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1474 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1498 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); in ufs_qcom_clk_scale_up_pre_change()
1537 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); in ufs_qcom_clk_scale_down_post_change()
1589 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1591 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1597 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1598 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1603 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1604 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1606 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1620 return -EINVAL; in ufs_qcom_testbus_config()
1623 return -EPERM; in ufs_qcom_testbus_config()
1625 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1682 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1683 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1685 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1686 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1707 host->testbus.select_major = j; in ufs_qcom_dump_testbus()
1710 host->testbus.select_minor = i; in ufs_qcom_dump_testbus()
1726 return -EINVAL; in ufs_qcom_dump_regs()
1730 return -ENOMEM; in ufs_qcom_dump_regs()
1733 regs[pos / 4] = readl(hba->res[id].base + offset + pos); in ufs_qcom_dump_regs()
1752 {0x0, 256 * 4, "MCQ HCI-0 ", RES_MCQ}, in ufs_qcom_dump_mcq_hci_regs()
1753 {0x400, 256 * 4, "MCQ HCI-1 ", RES_MCQ}, in ufs_qcom_dump_mcq_hci_regs()
1754 {0x0, 5 * 4, "MCQ VS-0 ", RES_MCQ_VS}, in ufs_qcom_dump_mcq_hci_regs()
1755 {0x0, 256 * 4, "MCQ SQD-0 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1756 {0x400, 256 * 4, "MCQ SQD-1 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1757 {0x800, 256 * 4, "MCQ SQD-2 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1758 {0xc00, 256 * 4, "MCQ SQD-3 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1759 {0x1000, 256 * 4, "MCQ SQD-4 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1760 {0x1400, 256 * 4, "MCQ SQD-5 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1761 {0x1800, 256 * 4, "MCQ SQD-6 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1762 {0x1c00, 256 * 4, "MCQ SQD-7 ", RES_MCQ_SQD}, in ufs_qcom_dump_mcq_hci_regs()
1779 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT)); in ufs_qcom_dump_dbg_regs()
1780 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT)); in ufs_qcom_dump_dbg_regs()
1782 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT)); in ufs_qcom_dump_dbg_regs()
1783 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT)); in ufs_qcom_dump_dbg_regs()
1785 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n", in ufs_qcom_dump_dbg_regs()
1807 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1831 if (hba->mcq_enabled) { in ufs_qcom_dump_dbg_regs()
1839 if (hba->mcq_enabled) in ufs_qcom_dump_dbg_regs()
1842 /* voluntarily yield the CPU as we are dumping too much data */ in ufs_qcom_dump_dbg_regs()
1850 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1851 * @hba: per-adapter instance
1860 if (!host->device_reset) in ufs_qcom_device_reset()
1861 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1864 * The UFS device shall detect reset pulses of 1us, sleep for 10us to in ufs_qcom_device_reset()
1881 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1882 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1883 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1884 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1886 hba->clk_scaling.suspend_on_no_request = true; in ufs_qcom_config_scaling_param()
1914 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1919 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1922 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1923 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1925 res->name); in ufs_qcom_mcq_config_resource()
1926 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1927 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1929 return -ENODEV; in ufs_qcom_mcq_config_resource()
1932 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1933 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1937 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1938 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1939 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1940 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1941 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1942 res->base = NULL; in ufs_qcom_mcq_config_resource()
1948 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1950 if (res->base) in ufs_qcom_mcq_config_resource()
1954 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1956 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1958 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1959 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1960 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1961 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1962 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1966 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1971 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1972 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1973 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1974 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1975 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1980 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1983 res->base = NULL; in ufs_qcom_mcq_config_resource()
1994 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1995 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1997 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1998 return -EINVAL; in ufs_qcom_op_runtime_config()
2001 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
2002 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
2003 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
2004 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
2005 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
2020 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
2022 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
2023 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
2025 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
2047 struct ufs_hba *hba = qi->hba; in ufs_qcom_mcq_esi_handler()
2048 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx]; in ufs_qcom_mcq_esi_handler()
2050 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx); in ufs_qcom_mcq_esi_handler()
2058 for (struct ufs_qcom_irq *q = uqi; q->irq; q++) in ufs_qcom_irq_free()
2059 devm_free_irq(q->hba->dev, q->irq, q->hba); in ufs_qcom_irq_free()
2061 platform_device_msi_free_irqs_all(uqi->hba->dev); in ufs_qcom_irq_free()
2062 devm_kfree(uqi->hba->dev, uqi); in ufs_qcom_irq_free()
2072 if (host->esi_enabled) in DEFINE_FREE()
2079 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in DEFINE_FREE()
2082 devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL); in DEFINE_FREE()
2084 return -ENOMEM; in DEFINE_FREE()
2088 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, in DEFINE_FREE()
2091 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in DEFINE_FREE()
2096 qi[idx].irq = msi_get_virq(hba->dev, idx); in DEFINE_FREE()
2100 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler, in DEFINE_FREE()
2101 IRQF_SHARED, "qcom-mcq-esi", qi + idx); in DEFINE_FREE()
2103 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in DEFINE_FREE()
2112 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in DEFINE_FREE()
2113 host->hw_ver.step == 0) { in DEFINE_FREE()
2114 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), in DEFINE_FREE()
2118 host->esi_enabled = true; in DEFINE_FREE()
2131 opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true); in ufs_qcom_opp_freq_to_clk_freq()
2133 dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq); in ufs_qcom_opp_freq_to_clk_freq()
2137 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_opp_freq_to_clk_freq()
2138 if (!strcmp(clki->name, name)) { in ufs_qcom_opp_freq_to_clk_freq()
2147 dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name); in ufs_qcom_opp_freq_to_clk_freq()
2164 if (!hba->use_pm_opp) in ufs_qcom_freq_to_gear_speed()
2187 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); in ufs_qcom_freq_to_gear_speed()
2191 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); in ufs_qcom_freq_to_gear_speed()
2195 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
2226 * ufs_qcom_probe - probe routine of the driver
2229 * Return: zero for success and non-zero for failure.
2234 struct device *dev = &pdev->dev; in ufs_qcom_probe()
2245 * ufs_qcom_remove - set driver_data of the device to NULL
2256 if (host->esi_enabled) in ufs_qcom_remove()
2257 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_remove()
2267 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2268 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2298 .name = "ufshcd-qcom",
2306 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");