Lines Matching full:hba
100 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
119 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init() local
120 struct blk_crypto_profile *profile = &hba->crypto_profile; in ufs_qcom_ice_init()
121 struct device *dev = hba->dev; in ufs_qcom_ice_init()
141 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); in ufs_qcom_ice_init()
159 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, in ufs_qcom_ice_init()
168 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
169 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; in ufs_qcom_ice_init()
175 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
183 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
193 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); in ufs_qcom_ice_keyslot_program() local
194 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_ice_keyslot_program()
201 ufshcd_hold(hba); in ufs_qcom_ice_keyslot_program()
208 ufshcd_release(hba); in ufs_qcom_ice_keyslot_program()
216 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); in ufs_qcom_ice_keyslot_evict() local
217 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_ice_keyslot_evict()
220 ufshcd_hold(hba); in ufs_qcom_ice_keyslot_evict()
222 ufshcd_release(hba); in ufs_qcom_ice_keyslot_evict()
279 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
293 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) in ufs_qcom_check_hibern8() argument
300 err = ufshcd_dme_get(hba, in ufs_qcom_check_hibern8()
316 err = ufshcd_dme_get(hba, in ufs_qcom_check_hibern8()
322 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
326 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
335 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
338 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
344 static int ufs_qcom_host_reset(struct ufs_hba *hba) in ufs_qcom_host_reset() argument
347 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_host_reset()
353 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
354 ufshcd_disable_irq(hba); in ufs_qcom_host_reset()
358 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
372 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
380 ufshcd_enable_irq(hba); in ufs_qcom_host_reset()
385 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) in ufs_qcom_get_hs_gear() argument
387 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_get_hs_gear()
390 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); in ufs_qcom_get_hs_gear()
396 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) in ufs_qcom_power_up_sequence() argument
398 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_power_up_sequence()
419 ret = ufs_qcom_host_reset(hba); in ufs_qcom_power_up_sequence()
431 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
443 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
466 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) in ufs_qcom_enable_hw_clk_gating() argument
468 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, in ufs_qcom_enable_hw_clk_gating()
472 ufshcd_readl(hba, REG_UFS_CFG2); in ufs_qcom_enable_hw_clk_gating()
475 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, in ufs_qcom_hce_enable_notify() argument
478 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_hce_enable_notify()
483 err = ufs_qcom_power_up_sequence(hba); in ufs_qcom_hce_enable_notify()
496 err = ufs_qcom_check_hibern8(hba); in ufs_qcom_hce_enable_notify()
497 ufs_qcom_enable_hw_clk_gating(hba); in ufs_qcom_hce_enable_notify()
501 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
511 * @hba: host controller instance
519 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, in ufs_qcom_cfg_timers() argument
523 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_cfg_timers()
534 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) in ufs_qcom_cfg_timers()
538 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); in ufs_qcom_cfg_timers()
542 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
558 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { in ufs_qcom_cfg_timers()
559 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
564 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
570 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, in ufs_qcom_link_startup_notify() argument
577 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, in ufs_qcom_link_startup_notify()
579 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
584 err = ufs_qcom_set_core_clk_ctrl(hba, true); in ufs_qcom_link_startup_notify()
586 dev_err(hba->dev, "cfg core clk ctrl failed\n"); in ufs_qcom_link_startup_notify()
594 err = ufshcd_disable_host_tx_lcc(hba); in ufs_qcom_link_startup_notify()
604 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) in ufs_qcom_device_reset_ctrl() argument
606 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_device_reset_ctrl()
615 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, in ufs_qcom_suspend() argument
618 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_suspend()
624 if (ufs_qcom_is_link_off(hba)) { in ufs_qcom_suspend()
634 ufs_qcom_device_reset_ctrl(hba, true); in ufs_qcom_suspend()
636 } else if (!ufs_qcom_is_link_active(hba)) { in ufs_qcom_suspend()
643 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) in ufs_qcom_resume() argument
645 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_resume()
649 if (ufs_qcom_is_link_off(hba)) { in ufs_qcom_resume()
652 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
661 } else if (!ufs_qcom_is_link_active(hba)) { in ufs_qcom_resume()
690 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
728 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
781 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, in ufs_qcom_pwr_change_notify() argument
786 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_pwr_change_notify()
799 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
810 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { in ufs_qcom_pwr_change_notify()
817 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_pwr_change_notify()
823 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
828 ufshcd_dme_configure_adapt(hba, in ufs_qcom_pwr_change_notify()
834 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, in ufs_qcom_pwr_change_notify()
837 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
854 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
866 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) in ufs_qcom_quirk_host_pa_saveconfigtime() argument
871 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
877 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
881 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) in ufs_qcom_apply_dev_quirks() argument
885 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
886 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); in ufs_qcom_apply_dev_quirks()
905 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) in ufs_qcom_fixup_dev_quirks() argument
907 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); in ufs_qcom_fixup_dev_quirks()
910 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) in ufs_qcom_get_ufs_hci_version() argument
917 * @hba: host controller instance
924 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) in ufs_qcom_advertise_quirks() argument
926 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_advertise_quirks()
927 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_advertise_quirks()
930 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
933 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
936 hba->quirks |= drvdata->quirks; in ufs_qcom_advertise_quirks()
961 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
970 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_set_phy_gear()
981 static void ufs_qcom_set_host_params(struct ufs_hba *hba) in ufs_qcom_set_host_params() argument
983 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_set_host_params()
989 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); in ufs_qcom_set_host_params()
992 static void ufs_qcom_set_caps(struct ufs_hba *hba) in ufs_qcom_set_caps() argument
994 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
995 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
996 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
997 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
998 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
999 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
1004 * @hba: host controller instance
1010 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, in ufs_qcom_setup_clocks() argument
1013 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_setup_clocks()
1028 if (!ufs_qcom_is_link_active(hba)) { in ufs_qcom_setup_clocks()
1037 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
1054 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
1065 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1082 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1110 * @hba: host controller instance
1118 static int ufs_qcom_init(struct ufs_hba *hba) in ufs_qcom_init() argument
1121 struct device *dev = hba->dev; in ufs_qcom_init()
1124 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_init()
1130 /* Make a two way bind between the qcom host and the hba */ in ufs_qcom_init()
1131 host->hba = hba; in ufs_qcom_init()
1132 ufshcd_set_variant(hba, host); in ufs_qcom_init()
1135 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1171 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1174 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1177 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1186 ufs_qcom_set_caps(hba); in ufs_qcom_init()
1187 ufs_qcom_advertise_quirks(hba); in ufs_qcom_init()
1188 ufs_qcom_set_host_params(hba); in ufs_qcom_init()
1195 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); in ufs_qcom_init()
1205 hba->spm_lvl = UFS_PM_LVL_5; in ufs_qcom_init()
1210 ufshcd_set_variant(hba, NULL); in ufs_qcom_init()
1215 static void ufs_qcom_exit(struct ufs_hba *hba) in ufs_qcom_exit() argument
1217 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_exit()
1227 * @hba: host controller instance
1233 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, in ufs_qcom_set_clk_40ns_cycles() argument
1236 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_set_clk_40ns_cycles()
1280 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", in ufs_qcom_set_clk_40ns_cycles()
1285 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); in ufs_qcom_set_clk_40ns_cycles()
1292 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); in ufs_qcom_set_clk_40ns_cycles()
1295 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) in ufs_qcom_set_core_clk_ctrl() argument
1297 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_set_core_clk_ctrl()
1298 struct list_head *head = &hba->clk_list_head; in ufs_qcom_set_core_clk_ctrl()
1317 err = ufshcd_dme_get(hba, in ufs_qcom_set_core_clk_ctrl()
1339 err = ufshcd_dme_set(hba, in ufs_qcom_set_core_clk_ctrl()
1346 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); in ufs_qcom_set_core_clk_ctrl()
1349 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_up_pre_change() argument
1351 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_clk_scale_up_pre_change()
1355 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, in ufs_qcom_clk_scale_up_pre_change()
1358 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); in ufs_qcom_clk_scale_up_pre_change()
1362 return ufs_qcom_set_core_clk_ctrl(hba, true); in ufs_qcom_clk_scale_up_pre_change()
1365 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_up_post_change() argument
1370 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_down_pre_change() argument
1375 err = ufshcd_dme_get(hba, in ufs_qcom_clk_scale_down_pre_change()
1383 err = ufshcd_dme_set(hba, in ufs_qcom_clk_scale_down_pre_change()
1391 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_down_post_change() argument
1394 return ufs_qcom_set_core_clk_ctrl(hba, false); in ufs_qcom_clk_scale_down_post_change()
1397 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, in ufs_qcom_clk_scale_notify() argument
1400 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_clk_scale_notify()
1404 if (!ufshcd_is_hba_active(hba)) in ufs_qcom_clk_scale_notify()
1408 err = ufshcd_uic_hibern8_enter(hba); in ufs_qcom_clk_scale_notify()
1412 err = ufs_qcom_clk_scale_up_pre_change(hba); in ufs_qcom_clk_scale_notify()
1414 err = ufs_qcom_clk_scale_down_pre_change(hba); in ufs_qcom_clk_scale_notify()
1417 ufshcd_uic_hibern8_exit(hba); in ufs_qcom_clk_scale_notify()
1422 err = ufs_qcom_clk_scale_up_post_change(hba); in ufs_qcom_clk_scale_notify()
1424 err = ufs_qcom_clk_scale_down_post_change(hba); in ufs_qcom_clk_scale_notify()
1428 ufshcd_uic_hibern8_exit(hba); in ufs_qcom_clk_scale_notify()
1433 ufshcd_uic_hibern8_exit(hba); in ufs_qcom_clk_scale_notify()
1441 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1443 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1456 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1534 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1537 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1545 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) in ufs_qcom_dump_dbg_regs() argument
1550 host = ufshcd_get_variant(hba); in ufs_qcom_dump_dbg_regs()
1552 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, in ufs_qcom_dump_dbg_regs()
1556 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); in ufs_qcom_dump_dbg_regs()
1558 reg = ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1560 ufshcd_writel(hba, reg, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1563 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); in ufs_qcom_dump_dbg_regs()
1566 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); in ufs_qcom_dump_dbg_regs()
1569 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); in ufs_qcom_dump_dbg_regs()
1572 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1575 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); in ufs_qcom_dump_dbg_regs()
1578 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); in ufs_qcom_dump_dbg_regs()
1581 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); in ufs_qcom_dump_dbg_regs()
1584 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); in ufs_qcom_dump_dbg_regs()
1587 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); in ufs_qcom_dump_dbg_regs()
1590 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); in ufs_qcom_dump_dbg_regs()
1593 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); in ufs_qcom_dump_dbg_regs()
1598 * @hba: per-adapter instance
1602 static int ufs_qcom_device_reset(struct ufs_hba *hba) in ufs_qcom_device_reset() argument
1604 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_device_reset()
1614 ufs_qcom_device_reset_ctrl(hba, true); in ufs_qcom_device_reset()
1617 ufs_qcom_device_reset_ctrl(hba, false); in ufs_qcom_device_reset()
1624 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, in ufs_qcom_config_scaling_param() argument
1633 hba->clk_scaling.suspend_on_no_request = true; in ufs_qcom_config_scaling_param()
1636 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, in ufs_qcom_config_scaling_param() argument
1659 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) in ufs_qcom_mcq_config_resource() argument
1661 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1666 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1669 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1674 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1680 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1684 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1686 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1695 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1701 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1706 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1707 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1713 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1718 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1720 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1727 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1735 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) in ufs_qcom_op_runtime_config() argument
1741 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1742 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1748 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1758 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) in ufs_qcom_get_hba_mac() argument
1764 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, in ufs_qcom_get_outstanding_cqs() argument
1767 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1780 struct ufs_hba *hba = dev_get_drvdata(dev); in ufs_qcom_write_msi_msg() local
1782 ufshcd_mcq_config_esi(hba, msg); in ufs_qcom_write_msi_msg()
1789 struct ufs_hba *hba = dev_get_drvdata(dev); in ufs_qcom_mcq_esi_handler() local
1791 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1793 ufshcd_mcq_write_cqis(hba, 0x1, id); in ufs_qcom_mcq_esi_handler()
1794 ufshcd_mcq_poll_cqe_lock(hba, hwq); in ufs_qcom_mcq_esi_handler()
1799 static int ufs_qcom_config_esi(struct ufs_hba *hba) in ufs_qcom_config_esi() argument
1801 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_config_esi()
1813 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1814 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1817 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1821 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1822 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1823 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1827 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1833 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1837 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1838 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1841 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1843 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1844 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_config_esi()
1848 ufshcd_rmwl(hba, ESI_VEC_MASK, in ufs_qcom_config_esi()
1851 ufshcd_mcq_enable_esi(hba); in ufs_qcom_config_esi()
1915 struct ufs_hba *hba = platform_get_drvdata(pdev); in ufs_qcom_remove() local
1916 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_remove()
1920 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_remove()