Lines Matching +full:ufs +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/arm-smccc.h>
18 #include <linux/phy/phy.h>
23 #include <ufs/ufshcd.h>
24 #include "ufshcd-pltfrm.h"
25 #include <ufs/ufs_quirks.h>
26 #include <ufs/unipro.h>
28 #include "ufs-mediatek.h"
29 #include "ufs-mediatek-sip.h"
34 #include "ufs-mediatek-trace.h"
52 { .compatible = "mediatek,mt8183-ufshci" },
61 "PHY Adapter Layer",
69 "PHY error on Lane 0",
70 "PHY error on Lane 1",
71 "PHY error on Lane 2",
72 "PHY error on Lane 3",
73 "Generic PHY Adapter Error. This should be the LINERESET indication"
99 return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE); in ufs_mtk_is_boost_crypt_enabled()
106 return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL); in ufs_mtk_is_va09_supported()
113 return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC); in ufs_mtk_is_broken_vcc()
120 return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO); in ufs_mtk_is_pmc_via_fastauto()
127 return (host->caps & UFS_MTK_CAP_TX_SKEW_FIX); in ufs_mtk_is_tx_skew_fix()
134 return (host->caps & UFS_MTK_CAP_RTFF_MTCMOS); in ufs_mtk_is_rtff_mtcmos()
141 return (host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM); in ufs_mtk_is_allow_vccqx_lpm()
186 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n", in ufs_mtk_crypto_enable()
188 hba->caps &= ~UFSHCD_CAP_CRYPTO; in ufs_mtk_crypto_enable()
197 reset_control_assert(host->hci_reset); in ufs_mtk_host_reset()
198 reset_control_assert(host->crypto_reset); in ufs_mtk_host_reset()
199 reset_control_assert(host->unipro_reset); in ufs_mtk_host_reset()
200 reset_control_assert(host->mphy_reset); in ufs_mtk_host_reset()
204 reset_control_deassert(host->unipro_reset); in ufs_mtk_host_reset()
205 reset_control_deassert(host->crypto_reset); in ufs_mtk_host_reset()
206 reset_control_deassert(host->hci_reset); in ufs_mtk_host_reset()
207 reset_control_deassert(host->mphy_reset); in ufs_mtk_host_reset()
210 if (host->mphy_reset) in ufs_mtk_host_reset()
218 *rc = devm_reset_control_get(hba->dev, str); in ufs_mtk_init_reset_control()
220 dev_info(hba->dev, "Failed to get reset control %s: %ld\n", in ufs_mtk_init_reset_control()
230 ufs_mtk_init_reset_control(hba, &host->hci_reset, in ufs_mtk_init_reset()
232 ufs_mtk_init_reset_control(hba, &host->unipro_reset, in ufs_mtk_init_reset()
234 ufs_mtk_init_reset_control(hba, &host->crypto_reset, in ufs_mtk_init_reset()
236 ufs_mtk_init_reset_control(hba, &host->mphy_reset, in ufs_mtk_init_reset()
246 if (host->unipro_lpm) { in ufs_mtk_hce_enable_notify()
247 hba->vps->hba_enable_delay_us = 0; in ufs_mtk_hce_enable_notify()
249 hba->vps->hba_enable_delay_us = 600; in ufs_mtk_hce_enable_notify()
253 if (hba->caps & UFSHCD_CAP_CRYPTO) in ufs_mtk_hce_enable_notify()
256 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) { in ufs_mtk_hce_enable_notify()
259 hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT; in ufs_mtk_hce_enable_notify()
260 hba->ahit = 0; in ufs_mtk_hce_enable_notify()
278 struct device *dev = hba->dev; in ufs_mtk_bind_mphy()
279 struct device_node *np = dev->of_node; in ufs_mtk_bind_mphy()
282 host->mphy = devm_of_phy_get_by_index(dev, np, 0); in ufs_mtk_bind_mphy()
284 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) { in ufs_mtk_bind_mphy()
286 * UFS driver might be probed before the phy driver does. in ufs_mtk_bind_mphy()
289 err = -EPROBE_DEFER; in ufs_mtk_bind_mphy()
291 "%s: required phy hasn't probed yet. err = %d\n", in ufs_mtk_bind_mphy()
293 } else if (IS_ERR(host->mphy)) { in ufs_mtk_bind_mphy()
294 err = PTR_ERR(host->mphy); in ufs_mtk_bind_mphy()
295 if (err != -ENODEV) { in ufs_mtk_bind_mphy()
296 dev_info(dev, "%s: PHY get failed %d\n", __func__, in ufs_mtk_bind_mphy()
302 host->mphy = NULL; in ufs_mtk_bind_mphy()
307 if (err == -ENODEV) in ufs_mtk_bind_mphy()
320 if (host->ref_clk_enabled == on) in ufs_mtk_setup_ref_clk()
328 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10); in ufs_mtk_setup_ref_clk()
345 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value); in ufs_mtk_setup_ref_clk()
347 ufs_mtk_ref_clk_notify(host->ref_clk_enabled, POST_CHANGE, res); in ufs_mtk_setup_ref_clk()
349 return -ETIMEDOUT; in ufs_mtk_setup_ref_clk()
352 host->ref_clk_enabled = on; in ufs_mtk_setup_ref_clk()
354 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10); in ufs_mtk_setup_ref_clk()
366 if (hba->dev_info.clk_gating_wait_us) { in ufs_mtk_setup_ref_clk_wait_us()
367 host->ref_clk_gating_wait_us = in ufs_mtk_setup_ref_clk_wait_us()
368 hba->dev_info.clk_gating_wait_us; in ufs_mtk_setup_ref_clk_wait_us()
370 host->ref_clk_gating_wait_us = gating_us; in ufs_mtk_setup_ref_clk_wait_us()
373 host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US; in ufs_mtk_setup_ref_clk_wait_us()
380 if (((host->ip_ver >> 16) & 0xFF) >= 0x36) { in ufs_mtk_dbg_sel()
428 dev_info(hba->dev, "wait idle tmo: 0x%x\n", val); in ufs_mtk_wait_idle_state()
451 return -ETIMEDOUT; in ufs_mtk_wait_link_state()
457 struct phy *mphy = host->mphy; in ufs_mtk_mphy_power_on()
461 if (!mphy || !(on ^ host->mphy_powered_on)) in ufs_mtk_mphy_power_on()
466 ret = regulator_enable(host->reg_va09); in ufs_mtk_mphy_power_on()
478 ret = regulator_disable(host->reg_va09); in ufs_mtk_mphy_power_on()
483 dev_info(hba->dev, in ufs_mtk_mphy_power_on()
488 host->mphy_powered_on = on; in ufs_mtk_mphy_power_on()
519 cfg = host->crypt; in ufs_mtk_boost_crypt()
520 volt = cfg->vcore_volt; in ufs_mtk_boost_crypt()
521 reg = cfg->reg_vcore; in ufs_mtk_boost_crypt()
523 ret = clk_prepare_enable(cfg->clk_crypt_mux); in ufs_mtk_boost_crypt()
525 dev_info(hba->dev, "clk_prepare_enable(): %d\n", in ufs_mtk_boost_crypt()
533 dev_info(hba->dev, in ufs_mtk_boost_crypt()
538 ret = clk_set_parent(cfg->clk_crypt_mux, in ufs_mtk_boost_crypt()
539 cfg->clk_crypt_perf); in ufs_mtk_boost_crypt()
541 dev_info(hba->dev, in ufs_mtk_boost_crypt()
547 ret = clk_set_parent(cfg->clk_crypt_mux, in ufs_mtk_boost_crypt()
548 cfg->clk_crypt_lp); in ufs_mtk_boost_crypt()
550 dev_info(hba->dev, in ufs_mtk_boost_crypt()
557 dev_info(hba->dev, in ufs_mtk_boost_crypt()
562 clk_disable_unprepare(cfg->clk_crypt_mux); in ufs_mtk_boost_crypt()
570 ret = ufs_mtk_get_host_clk(hba->dev, name, clk); in ufs_mtk_init_host_clk()
572 dev_info(hba->dev, "%s: failed to get %s: %d", __func__, in ufs_mtk_init_host_clk()
583 struct device *dev = hba->dev; in ufs_mtk_init_boost_crypt()
587 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)), in ufs_mtk_init_boost_crypt()
589 if (!host->crypt) in ufs_mtk_init_boost_crypt()
592 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore"); in ufs_mtk_init_boost_crypt()
594 dev_info(dev, "failed to get dvfsrc-vcore: %ld", in ufs_mtk_init_boost_crypt()
599 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min", in ufs_mtk_init_boost_crypt()
601 dev_info(dev, "failed to get boost-crypt-vcore-min"); in ufs_mtk_init_boost_crypt()
605 cfg = host->crypt; in ufs_mtk_init_boost_crypt()
607 &cfg->clk_crypt_mux)) in ufs_mtk_init_boost_crypt()
611 &cfg->clk_crypt_lp)) in ufs_mtk_init_boost_crypt()
615 &cfg->clk_crypt_perf)) in ufs_mtk_init_boost_crypt()
618 cfg->reg_vcore = reg; in ufs_mtk_init_boost_crypt()
619 cfg->vcore_volt = volt; in ufs_mtk_init_boost_crypt()
620 host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE; in ufs_mtk_init_boost_crypt()
630 host->reg_va09 = regulator_get(hba->dev, "va09"); in ufs_mtk_init_va09_pwr_ctrl()
631 if (IS_ERR(host->reg_va09)) in ufs_mtk_init_va09_pwr_ctrl()
632 dev_info(hba->dev, "failed to get va09"); in ufs_mtk_init_va09_pwr_ctrl()
634 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL; in ufs_mtk_init_va09_pwr_ctrl()
640 struct device_node *np = hba->dev->of_node; in ufs_mtk_init_host_caps()
642 if (of_property_read_bool(np, "mediatek,ufs-boost-crypt")) in ufs_mtk_init_host_caps()
645 if (of_property_read_bool(np, "mediatek,ufs-support-va09")) in ufs_mtk_init_host_caps()
648 if (of_property_read_bool(np, "mediatek,ufs-disable-ah8")) in ufs_mtk_init_host_caps()
649 host->caps |= UFS_MTK_CAP_DISABLE_AH8; in ufs_mtk_init_host_caps()
651 if (of_property_read_bool(np, "mediatek,ufs-broken-vcc")) in ufs_mtk_init_host_caps()
652 host->caps |= UFS_MTK_CAP_BROKEN_VCC; in ufs_mtk_init_host_caps()
654 if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto")) in ufs_mtk_init_host_caps()
655 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO; in ufs_mtk_init_host_caps()
657 if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix")) in ufs_mtk_init_host_caps()
658 host->caps |= UFS_MTK_CAP_TX_SKEW_FIX; in ufs_mtk_init_host_caps()
660 if (of_property_read_bool(np, "mediatek,ufs-disable-mcq")) in ufs_mtk_init_host_caps()
661 host->caps |= UFS_MTK_CAP_DISABLE_MCQ; in ufs_mtk_init_host_caps()
663 if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos")) in ufs_mtk_init_host_caps()
664 host->caps |= UFS_MTK_CAP_RTFF_MTCMOS; in ufs_mtk_init_host_caps()
666 dev_info(hba->dev, "caps: 0x%x", host->caps); in ufs_mtk_init_host_caps()
679 phy_power_on(host->mphy); in ufs_mtk_pwr_ctrl()
687 phy_power_off(host->mphy); in ufs_mtk_pwr_ctrl()
696 if (!hba->mcq_enabled) in ufs_mtk_mcq_disable_irq()
699 if (host->mcq_nr_intr == 0) in ufs_mtk_mcq_disable_irq()
702 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_mcq_disable_irq()
703 irq = host->mcq_intr_info[i].irq; in ufs_mtk_mcq_disable_irq()
706 host->is_mcq_intr_enabled = false; in ufs_mtk_mcq_disable_irq()
714 if (!hba->mcq_enabled) in ufs_mtk_mcq_enable_irq()
717 if (host->mcq_nr_intr == 0) in ufs_mtk_mcq_enable_irq()
720 if (host->is_mcq_intr_enabled == true) in ufs_mtk_mcq_enable_irq()
723 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_mcq_enable_irq()
724 irq = host->mcq_intr_info[i].irq; in ufs_mtk_mcq_enable_irq()
727 host->is_mcq_intr_enabled = true; in ufs_mtk_mcq_enable_irq()
731 * ufs_mtk_setup_clocks - enables/disable clocks
736 * Return: 0 on success, non-zero on failure.
760 * Gate ref-clk and poweroff mphy if link state is in in ufs_mtk_setup_clocks()
761 * OFF or Hibern8 by either Auto-Hibern8 or in ufs_mtk_setup_clocks()
787 if (host->hw_ver.major) in ufs_mtk_get_controller_version()
791 host->hw_ver.major = 2; in ufs_mtk_get_controller_version()
796 host->hw_ver.major = 3; in ufs_mtk_get_controller_version()
801 if (hba->ufs_version < ufshci_version(3, 0)) in ufs_mtk_get_controller_version()
802 hba->ufs_version = ufshci_version(3, 0); in ufs_mtk_get_controller_version()
809 return hba->ufs_version; in ufs_mtk_get_ufs_hci_version()
813 * ufs_mtk_init_clocks - Init mtk driver private clocks
820 struct list_head *head = &hba->clk_list_head; in ufs_mtk_init_clocks()
821 struct ufs_mtk_clk *mclk = &host->mclk; in ufs_mtk_init_clocks()
830 if (!strcmp(clki->name, "ufs_sel")) { in ufs_mtk_init_clocks()
831 host->mclk.ufs_sel_clki = clki; in ufs_mtk_init_clocks()
832 } else if (!strcmp(clki->name, "ufs_sel_max_src")) { in ufs_mtk_init_clocks()
833 host->mclk.ufs_sel_max_clki = clki; in ufs_mtk_init_clocks()
834 clk_disable_unprepare(clki->clk); in ufs_mtk_init_clocks()
835 list_del(&clki->list); in ufs_mtk_init_clocks()
836 } else if (!strcmp(clki->name, "ufs_sel_min_src")) { in ufs_mtk_init_clocks()
837 host->mclk.ufs_sel_min_clki = clki; in ufs_mtk_init_clocks()
838 clk_disable_unprepare(clki->clk); in ufs_mtk_init_clocks()
839 list_del(&clki->list); in ufs_mtk_init_clocks()
843 if (!mclk->ufs_sel_clki || !mclk->ufs_sel_max_clki || in ufs_mtk_init_clocks()
844 !mclk->ufs_sel_min_clki) { in ufs_mtk_init_clocks()
845 hba->caps &= ~UFSHCD_CAP_CLK_SCALING; in ufs_mtk_init_clocks()
846 dev_info(hba->dev, in ufs_mtk_init_clocks()
847 "%s: Clk-scaling not ready. Feature disabled.", in ufs_mtk_init_clocks()
855 struct ufs_vreg_info *info = &hba->vreg_info; in ufs_mtk_vreg_fix_vcc()
856 struct device_node *np = hba->dev->of_node; in ufs_mtk_vreg_fix_vcc()
857 struct device *dev = hba->dev; in ufs_mtk_vreg_fix_vcc()
862 if (hba->vreg_info.vcc) in ufs_mtk_vreg_fix_vcc()
865 if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) { in ufs_mtk_vreg_fix_vcc()
868 snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1); in ufs_mtk_vreg_fix_vcc()
870 return -ENODEV; in ufs_mtk_vreg_fix_vcc()
871 } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) { in ufs_mtk_vreg_fix_vcc()
872 ver = (hba->dev_info.wspecversion & 0xF00) >> 8; in ufs_mtk_vreg_fix_vcc()
873 snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver); in ufs_mtk_vreg_fix_vcc()
878 err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false); in ufs_mtk_vreg_fix_vcc()
882 err = ufshcd_get_vreg(dev, info->vcc); in ufs_mtk_vreg_fix_vcc()
886 err = regulator_enable(info->vcc->reg); in ufs_mtk_vreg_fix_vcc()
888 info->vcc->enabled = true; in ufs_mtk_vreg_fix_vcc()
897 struct ufs_vreg_info *info = &hba->vreg_info; in ufs_mtk_vreg_fix_vccqx()
900 if (hba->dev_info.wspecversion >= 0x0300) { in ufs_mtk_vreg_fix_vccqx()
901 vreg_on = &info->vccq; in ufs_mtk_vreg_fix_vccqx()
902 vreg_off = &info->vccq2; in ufs_mtk_vreg_fix_vccqx()
904 vreg_on = &info->vccq2; in ufs_mtk_vreg_fix_vccqx()
905 vreg_off = &info->vccq; in ufs_mtk_vreg_fix_vccqx()
909 (*vreg_on)->always_on = true; in ufs_mtk_vreg_fix_vccqx()
912 regulator_disable((*vreg_off)->reg); in ufs_mtk_vreg_fix_vccqx()
913 devm_kfree(hba->dev, (*vreg_off)->name); in ufs_mtk_vreg_fix_vccqx()
914 devm_kfree(hba->dev, *vreg_off); in ufs_mtk_vreg_fix_vccqx()
926 host->mcq_nr_intr = UFSHCD_MAX_Q_NR; in ufs_mtk_init_mcq_irq()
927 pdev = container_of(hba->dev, struct platform_device, dev); in ufs_mtk_init_mcq_irq()
929 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ) in ufs_mtk_init_mcq_irq()
932 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_init_mcq_irq()
936 host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ; in ufs_mtk_init_mcq_irq()
939 host->mcq_intr_info[i].hba = hba; in ufs_mtk_init_mcq_irq()
940 host->mcq_intr_info[i].irq = irq; in ufs_mtk_init_mcq_irq()
941 dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq); in ufs_mtk_init_mcq_irq()
947 for (i = 0; i < host->mcq_nr_intr; i++) in ufs_mtk_init_mcq_irq()
948 host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ; in ufs_mtk_init_mcq_irq()
950 host->mcq_nr_intr = 0; in ufs_mtk_init_mcq_irq()
954 * ufs_mtk_init - find other essential mmio bases
957 * Binds PHY with controller and powers up PHY enabling clocks
960 * Return: -EPROBE_DEFER if binding fails, returns negative error
961 * on phy power up failure and returns zero on success.
966 struct device *dev = hba->dev; in ufs_mtk_init()
968 struct Scsi_Host *shost = hba->host; in ufs_mtk_init()
974 err = -ENOMEM; in ufs_mtk_init()
975 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__); in ufs_mtk_init()
979 host->hba = hba; in ufs_mtk_init()
984 err = -EINVAL; in ufs_mtk_init()
1000 if (host->mphy_reset) in ufs_mtk_init()
1004 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_mtk_init()
1006 /* Enable clock-gating */ in ufs_mtk_init()
1007 hba->caps |= UFSHCD_CAP_CLK_GATING; in ufs_mtk_init()
1010 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_mtk_init()
1013 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_mtk_init()
1016 hba->caps |= UFSHCD_CAP_CLK_SCALING; in ufs_mtk_init()
1019 shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS; in ufs_mtk_init()
1021 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL; in ufs_mtk_init()
1022 hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR; in ufs_mtk_init()
1023 hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC; in ufs_mtk_init()
1024 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80); in ufs_mtk_init()
1026 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) in ufs_mtk_init()
1027 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_mtk_init()
1029 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ) in ufs_mtk_init()
1030 hba->quirks |= UFSHCD_QUIRK_BROKEN_LSDBS_CAP; in ufs_mtk_init()
1037 * phy clock setup is skipped. in ufs_mtk_init()
1039 * Enable phy clocks specifically here. in ufs_mtk_init()
1053 host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER); in ufs_mtk_init()
1069 if (dev_req_params->hs_rate == hba->pwr_info.hs_rate) in ufs_mtk_pmc_via_fastauto()
1072 if (dev_req_params->pwr_tx != FAST_MODE && in ufs_mtk_pmc_via_fastauto()
1073 dev_req_params->gear_tx < UFS_HS_G4) in ufs_mtk_pmc_via_fastauto()
1076 if (dev_req_params->pwr_rx != FAST_MODE && in ufs_mtk_pmc_via_fastauto()
1077 dev_req_params->gear_rx < UFS_HS_G4) in ufs_mtk_pmc_via_fastauto()
1109 dev_req_params->lane_tx); in ufs_mtk_pre_pwr_change()
1111 dev_req_params->lane_rx); in ufs_mtk_pre_pwr_change()
1113 dev_req_params->hs_rate); in ufs_mtk_pre_pwr_change()
1122 dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n", in ufs_mtk_pre_pwr_change()
1127 if (host->hw_ver.major >= 3) { in ufs_mtk_pre_pwr_change()
1129 dev_req_params->gear_tx, in ufs_mtk_pre_pwr_change()
1151 ret = -EINVAL; in ufs_mtk_pwr_change_notify()
1168 * Forcibly set as non-LPM mode if UIC commands is failed in ufs_mtk_unipro_set_lpm()
1169 * to use default hba_enable_delay_us value for re-enabling in ufs_mtk_unipro_set_lpm()
1172 host->unipro_lpm = lpm; in ufs_mtk_unipro_set_lpm()
1215 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) in ufs_mtk_setup_clk_gating()
1217 hba->ahit); in ufs_mtk_setup_clk_gating()
1220 ufshcd_clkgate_delay_set(hba->dev, ah_ms + 5); in ufs_mtk_setup_clk_gating()
1231 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) | in ufs_mtk_post_link()
1250 ret = -EINVAL; in ufs_mtk_link_startup_notify()
1267 * The reset signal is active low. UFS devices shall detect in ufs_mtk_device_reset()
1280 dev_info(hba->dev, "device reset done\n"); in ufs_mtk_device_reset()
1305 dev_warn(hba->dev, "exit h8 state fail, err=%d\n", err); in ufs_mtk_link_set_hpm()
1314 if (hba->mcq_enabled) { in ufs_mtk_link_set_hpm()
1317 ufshcd_mcq_config_mac(hba, hba->nutrs); in ufs_mtk_link_set_hpm()
1347 if (hba->vreg_info.vccq) in ufs_mtk_vccqx_set_lpm()
1348 vccqx = hba->vreg_info.vccq; in ufs_mtk_vccqx_set_lpm()
1350 vccqx = hba->vreg_info.vccq2; in ufs_mtk_vccqx_set_lpm()
1352 regulator_set_mode(vccqx->reg, in ufs_mtk_vccqx_set_lpm()
1361 (unsigned long)hba->dev_info.wspecversion, in ufs_mtk_vsx_set_lpm()
1374 if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2) in ufs_mtk_dev_vreg_set_lpm()
1377 /* VCC is always-on, control vsx only */ in ufs_mtk_dev_vreg_set_lpm()
1378 if (!hba->vreg_info.vcc) in ufs_mtk_dev_vreg_set_lpm()
1382 if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) { in ufs_mtk_dev_vreg_set_lpm()
1405 /* disable auto-hibern8 */ in ufs_mtk_auto_hibern8_disable()
1408 /* wait host return to idle state when auto-hibern8 off */ in ufs_mtk_auto_hibern8_disable()
1413 dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret); in ufs_mtk_auto_hibern8_disable()
1437 * ufshcd_suspend() re-enabling regulators while vreg is still in ufs_mtk_suspend()
1438 * in low-power mode. in ufs_mtk_suspend()
1458 return -EAGAIN; in ufs_mtk_suspend()
1466 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) in ufs_mtk_resume()
1496 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4, in ufs_mtk_dbg_register_dump()
1506 struct ufs_dev_info *dev_info = &hba->dev_info; in ufs_mtk_apply_dev_quirks()
1507 u16 mid = dev_info->wmanufacturerid; in ufs_mtk_apply_dev_quirks()
1515 (STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1516 STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1517 STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1518 STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1519 STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1520 STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) { in ufs_mtk_apply_dev_quirks()
1546 if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc && in ufs_mtk_fixup_dev_quirks()
1547 (hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)) { in ufs_mtk_fixup_dev_quirks()
1548 hba->vreg_info.vcc->always_on = true; in ufs_mtk_fixup_dev_quirks()
1550 * VCC will be kept always-on thus we don't in ufs_mtk_fixup_dev_quirks()
1553 hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | in ufs_mtk_fixup_dev_quirks()
1572 dev_info(hba->dev, in ufs_mtk_event_notify()
1580 dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); in ufs_mtk_event_notify()
1585 dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); in ufs_mtk_event_notify()
1594 hba->clk_scaling.min_gear = UFS_HS_G4; in ufs_mtk_config_scaling_param()
1596 hba->vps->devfreq_profile.polling_ms = 200; in ufs_mtk_config_scaling_param()
1597 hba->vps->ondemand_data.upthreshold = 50; in ufs_mtk_config_scaling_param()
1598 hba->vps->ondemand_data.downdifferential = 20; in ufs_mtk_config_scaling_param()
1602 * ufs_mtk_clk_scale - Internal clk scaling operation
1605 * The ufs_sel downstream to ufs_ck which feeds directly to UFS hardware.
1616 struct ufs_mtk_clk *mclk = &host->mclk; in ufs_mtk_clk_scale()
1617 struct ufs_clk_info *clki = mclk->ufs_sel_clki; in ufs_mtk_clk_scale()
1620 ret = clk_prepare_enable(clki->clk); in ufs_mtk_clk_scale()
1622 dev_info(hba->dev, in ufs_mtk_clk_scale()
1628 ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); in ufs_mtk_clk_scale()
1629 clki->curr_freq = clki->max_freq; in ufs_mtk_clk_scale()
1631 ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk); in ufs_mtk_clk_scale()
1632 clki->curr_freq = clki->min_freq; in ufs_mtk_clk_scale()
1636 dev_info(hba->dev, in ufs_mtk_clk_scale()
1640 clk_disable_unprepare(clki->clk); in ufs_mtk_clk_scale()
1642 trace_ufs_mtk_clk_scale(clki->name, scale_up, clk_get_rate(clki->clk)); in ufs_mtk_clk_scale()
1667 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ) in ufs_mtk_get_hba_mac()
1668 return -EPERM; in ufs_mtk_get_hba_mac()
1678 hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD; in ufs_mtk_op_runtime_config()
1679 hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS; in ufs_mtk_op_runtime_config()
1680 hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD; in ufs_mtk_op_runtime_config()
1681 hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS; in ufs_mtk_op_runtime_config()
1684 opr = &hba->mcq_opr[i]; in ufs_mtk_op_runtime_config()
1685 opr->stride = REG_UFS_MCQ_STRIDE; in ufs_mtk_op_runtime_config()
1686 opr->base = hba->mmio_base + opr->offset; in ufs_mtk_op_runtime_config()
1697 if (!host->mcq_nr_intr) { in ufs_mtk_mcq_config_resource()
1698 dev_info(hba->dev, "IRQs not ready. MCQ disabled."); in ufs_mtk_mcq_config_resource()
1699 return -EINVAL; in ufs_mtk_mcq_config_resource()
1702 hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities); in ufs_mtk_mcq_config_resource()
1709 struct ufs_hba *hba = mcq_intr_info->hba; in ufs_mtk_mcq_intr()
1712 int qid = mcq_intr_info->qid; in ufs_mtk_mcq_intr()
1714 hwq = &hba->uhq[qid]; in ufs_mtk_mcq_intr()
1732 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_config_mcq_irq()
1733 irq = host->mcq_intr_info[i].irq; in ufs_mtk_config_mcq_irq()
1735 dev_err(hba->dev, "invalid irq. %d\n", i); in ufs_mtk_config_mcq_irq()
1736 return -ENOPARAM; in ufs_mtk_config_mcq_irq()
1739 host->mcq_intr_info[i].qid = i; in ufs_mtk_config_mcq_irq()
1740 ret = devm_request_irq(hba->dev, irq, ufs_mtk_mcq_intr, 0, UFSHCD, in ufs_mtk_config_mcq_irq()
1741 &host->mcq_intr_info[i]); in ufs_mtk_config_mcq_irq()
1743 dev_dbg(hba->dev, "request irq %d intr %s\n", irq, ret ? "failed" : ""); in ufs_mtk_config_mcq_irq()
1746 dev_err(hba->dev, "Cannot request irq %d\n", ret); in ufs_mtk_config_mcq_irq()
1759 if (!host->mcq_set_intr) { in ufs_mtk_config_mcq()
1769 host->mcq_set_intr = true; in ufs_mtk_config_mcq()
1784 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
1786 * The variant operations configure the necessary controller and PHY
1815 * ufs_mtk_probe - probe routine of the driver
1818 * Return: zero for success and non-zero for failure.
1823 struct device *dev = &pdev->dev; in ufs_mtk_probe()
1829 "ti,syscon-reset"); in ufs_mtk_probe()
1831 dev_notice(dev, "find ti,syscon-reset fail\n"); in ufs_mtk_probe()
1839 link = device_link_add(dev, &reset_pdev->dev, in ufs_mtk_probe()
1841 put_device(&reset_pdev->dev); in ufs_mtk_probe()
1847 if (link->status == DL_STATE_DORMANT) { in ufs_mtk_probe()
1848 err = -EPROBE_DEFER; in ufs_mtk_probe()
1865 * ufs_mtk_remove - set driver_data of the device to NULL
1874 pm_runtime_get_sync(&(pdev)->dev); in ufs_mtk_remove()
1957 .name = "ufshcd-mtk",
1965 MODULE_DESCRIPTION("MediaTek UFS Host Driver");