Lines Matching +full:cpu +full:- +full:ufs
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/arm-smccc.h>
23 #include <ufs/ufshcd.h>
24 #include "ufshcd-pltfrm.h"
25 #include <ufs/ufs_quirks.h>
26 #include <ufs/unipro.h>
28 #include "ufs-mediatek.h"
29 #include "ufs-mediatek-sip.h"
35 #include "ufs-mediatek-trace.h"
52 { .compatible = "mediatek,mt8183-ufshci" },
53 { .compatible = "mediatek,mt8195-ufshci" },
100 return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE; in ufs_mtk_is_boost_crypt_enabled()
107 return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL; in ufs_mtk_is_va09_supported()
114 return host->caps & UFS_MTK_CAP_BROKEN_VCC; in ufs_mtk_is_broken_vcc()
121 return host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO; in ufs_mtk_is_pmc_via_fastauto()
128 return host->caps & UFS_MTK_CAP_TX_SKEW_FIX; in ufs_mtk_is_tx_skew_fix()
135 return host->caps & UFS_MTK_CAP_RTFF_MTCMOS; in ufs_mtk_is_rtff_mtcmos()
142 return host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM; in ufs_mtk_is_allow_vccqx_lpm()
148 struct ufs_mtk_clk *mclk = &host->mclk; in ufs_mtk_is_clk_scale_ready()
150 return mclk->ufs_sel_clki && in ufs_mtk_is_clk_scale_ready()
151 mclk->ufs_sel_max_clki && in ufs_mtk_is_clk_scale_ready()
152 mclk->ufs_sel_min_clki; in ufs_mtk_is_clk_scale_ready()
197 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n", in ufs_mtk_crypto_enable()
199 hba->caps &= ~UFSHCD_CAP_CRYPTO; in ufs_mtk_crypto_enable()
208 reset_control_assert(host->hci_reset); in ufs_mtk_host_reset()
209 reset_control_assert(host->crypto_reset); in ufs_mtk_host_reset()
210 reset_control_assert(host->unipro_reset); in ufs_mtk_host_reset()
211 reset_control_assert(host->mphy_reset); in ufs_mtk_host_reset()
215 reset_control_deassert(host->unipro_reset); in ufs_mtk_host_reset()
216 reset_control_deassert(host->crypto_reset); in ufs_mtk_host_reset()
217 reset_control_deassert(host->hci_reset); in ufs_mtk_host_reset()
218 reset_control_deassert(host->mphy_reset); in ufs_mtk_host_reset()
221 if (host->mphy_reset) in ufs_mtk_host_reset()
229 *rc = devm_reset_control_get(hba->dev, str); in ufs_mtk_init_reset_control()
231 dev_info(hba->dev, "Failed to get reset control %s: %ld\n", in ufs_mtk_init_reset_control()
241 ufs_mtk_init_reset_control(hba, &host->hci_reset, in ufs_mtk_init_reset()
243 ufs_mtk_init_reset_control(hba, &host->unipro_reset, in ufs_mtk_init_reset()
245 ufs_mtk_init_reset_control(hba, &host->crypto_reset, in ufs_mtk_init_reset()
247 ufs_mtk_init_reset_control(hba, &host->mphy_reset, in ufs_mtk_init_reset()
257 if (host->unipro_lpm) { in ufs_mtk_hce_enable_notify()
258 hba->vps->hba_enable_delay_us = 0; in ufs_mtk_hce_enable_notify()
260 hba->vps->hba_enable_delay_us = 600; in ufs_mtk_hce_enable_notify()
264 if (hba->caps & UFSHCD_CAP_CRYPTO) in ufs_mtk_hce_enable_notify()
267 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) { in ufs_mtk_hce_enable_notify()
270 hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT; in ufs_mtk_hce_enable_notify()
271 hba->ahit = 0; in ufs_mtk_hce_enable_notify()
282 if (host->legacy_ip_ver) in ufs_mtk_hce_enable_notify()
286 if (host->ip_ver >= IP_VER_MT6989) { in ufs_mtk_hce_enable_notify()
291 if (host->ip_ver >= IP_VER_MT6991_A0) { in ufs_mtk_hce_enable_notify()
292 /* Enable multi-rtt */ in ufs_mtk_hce_enable_notify()
305 struct device *dev = hba->dev; in ufs_mtk_bind_mphy()
306 struct device_node *np = dev->of_node; in ufs_mtk_bind_mphy()
309 host->mphy = devm_of_phy_get_by_index(dev, np, 0); in ufs_mtk_bind_mphy()
311 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) { in ufs_mtk_bind_mphy()
313 * UFS driver might be probed before the phy driver does. in ufs_mtk_bind_mphy()
316 err = -EPROBE_DEFER; in ufs_mtk_bind_mphy()
320 } else if (IS_ERR(host->mphy)) { in ufs_mtk_bind_mphy()
321 err = PTR_ERR(host->mphy); in ufs_mtk_bind_mphy()
322 if (err != -ENODEV) { in ufs_mtk_bind_mphy()
329 host->mphy = NULL; in ufs_mtk_bind_mphy()
334 if (err == -ENODEV) in ufs_mtk_bind_mphy()
347 if (host->ref_clk_enabled == on) in ufs_mtk_setup_ref_clk()
355 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10); in ufs_mtk_setup_ref_clk()
372 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value); in ufs_mtk_setup_ref_clk()
383 host->ref_clk_enabled = false; in ufs_mtk_setup_ref_clk()
385 return -ETIMEDOUT; in ufs_mtk_setup_ref_clk()
388 host->ref_clk_enabled = on; in ufs_mtk_setup_ref_clk()
390 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10); in ufs_mtk_setup_ref_clk()
402 if (hba->dev_info.clk_gating_wait_us) { in ufs_mtk_setup_ref_clk_wait_us()
403 host->ref_clk_gating_wait_us = in ufs_mtk_setup_ref_clk_wait_us()
404 hba->dev_info.clk_gating_wait_us; in ufs_mtk_setup_ref_clk_wait_us()
406 host->ref_clk_gating_wait_us = gating_us; in ufs_mtk_setup_ref_clk_wait_us()
409 host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US; in ufs_mtk_setup_ref_clk_wait_us()
416 if (!host->legacy_ip_ver && host->ip_ver >= IP_VER_MT6983) { in ufs_mtk_dbg_sel()
444 if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { in ufs_mtk_wait_idle_state()
470 dev_info(hba->dev, "wait idle tmo: 0x%x\n", val); in ufs_mtk_wait_idle_state()
471 return -ETIMEDOUT; in ufs_mtk_wait_idle_state()
488 if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { in ufs_mtk_wait_link_state()
504 return -ETIMEDOUT; in ufs_mtk_wait_link_state()
510 struct phy *mphy = host->mphy; in ufs_mtk_mphy_power_on()
514 if (!mphy || !(on ^ host->mphy_powered_on)) in ufs_mtk_mphy_power_on()
519 ret = regulator_enable(host->reg_va09); in ufs_mtk_mphy_power_on()
531 ret = regulator_disable(host->reg_va09); in ufs_mtk_mphy_power_on()
536 dev_info(hba->dev, in ufs_mtk_mphy_power_on()
541 host->mphy_powered_on = on; in ufs_mtk_mphy_power_on()
572 cfg = host->crypt; in ufs_mtk_boost_crypt()
573 volt = cfg->vcore_volt; in ufs_mtk_boost_crypt()
574 reg = cfg->reg_vcore; in ufs_mtk_boost_crypt()
576 ret = clk_prepare_enable(cfg->clk_crypt_mux); in ufs_mtk_boost_crypt()
578 dev_info(hba->dev, "clk_prepare_enable(): %d\n", in ufs_mtk_boost_crypt()
586 dev_info(hba->dev, in ufs_mtk_boost_crypt()
591 ret = clk_set_parent(cfg->clk_crypt_mux, in ufs_mtk_boost_crypt()
592 cfg->clk_crypt_perf); in ufs_mtk_boost_crypt()
594 dev_info(hba->dev, in ufs_mtk_boost_crypt()
600 ret = clk_set_parent(cfg->clk_crypt_mux, in ufs_mtk_boost_crypt()
601 cfg->clk_crypt_lp); in ufs_mtk_boost_crypt()
603 dev_info(hba->dev, in ufs_mtk_boost_crypt()
610 dev_info(hba->dev, in ufs_mtk_boost_crypt()
615 clk_disable_unprepare(cfg->clk_crypt_mux); in ufs_mtk_boost_crypt()
623 ret = ufs_mtk_get_host_clk(hba->dev, name, clk); in ufs_mtk_init_host_clk()
625 dev_info(hba->dev, "%s: failed to get %s: %d", __func__, in ufs_mtk_init_host_clk()
636 struct device *dev = hba->dev; in ufs_mtk_init_boost_crypt()
640 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)), in ufs_mtk_init_boost_crypt()
642 if (!host->crypt) in ufs_mtk_init_boost_crypt()
645 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore"); in ufs_mtk_init_boost_crypt()
647 dev_info(dev, "failed to get dvfsrc-vcore: %ld", in ufs_mtk_init_boost_crypt()
652 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min", in ufs_mtk_init_boost_crypt()
654 dev_info(dev, "failed to get boost-crypt-vcore-min"); in ufs_mtk_init_boost_crypt()
658 cfg = host->crypt; in ufs_mtk_init_boost_crypt()
660 &cfg->clk_crypt_mux)) in ufs_mtk_init_boost_crypt()
664 &cfg->clk_crypt_lp)) in ufs_mtk_init_boost_crypt()
668 &cfg->clk_crypt_perf)) in ufs_mtk_init_boost_crypt()
671 cfg->reg_vcore = reg; in ufs_mtk_init_boost_crypt()
672 cfg->vcore_volt = volt; in ufs_mtk_init_boost_crypt()
673 host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE; in ufs_mtk_init_boost_crypt()
683 host->reg_va09 = regulator_get(hba->dev, "va09"); in ufs_mtk_init_va09_pwr_ctrl()
684 if (IS_ERR(host->reg_va09)) in ufs_mtk_init_va09_pwr_ctrl()
685 dev_info(hba->dev, "failed to get va09"); in ufs_mtk_init_va09_pwr_ctrl()
687 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL; in ufs_mtk_init_va09_pwr_ctrl()
693 struct device_node *np = hba->dev->of_node; in ufs_mtk_init_host_caps()
695 if (of_property_read_bool(np, "mediatek,ufs-boost-crypt")) in ufs_mtk_init_host_caps()
698 if (of_property_read_bool(np, "mediatek,ufs-support-va09")) in ufs_mtk_init_host_caps()
701 if (of_property_read_bool(np, "mediatek,ufs-disable-ah8")) in ufs_mtk_init_host_caps()
702 host->caps |= UFS_MTK_CAP_DISABLE_AH8; in ufs_mtk_init_host_caps()
704 if (of_property_read_bool(np, "mediatek,ufs-broken-vcc")) in ufs_mtk_init_host_caps()
705 host->caps |= UFS_MTK_CAP_BROKEN_VCC; in ufs_mtk_init_host_caps()
707 if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto")) in ufs_mtk_init_host_caps()
708 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO; in ufs_mtk_init_host_caps()
710 if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix")) in ufs_mtk_init_host_caps()
711 host->caps |= UFS_MTK_CAP_TX_SKEW_FIX; in ufs_mtk_init_host_caps()
713 if (of_property_read_bool(np, "mediatek,ufs-disable-mcq")) in ufs_mtk_init_host_caps()
714 host->caps |= UFS_MTK_CAP_DISABLE_MCQ; in ufs_mtk_init_host_caps()
716 if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos")) in ufs_mtk_init_host_caps()
717 host->caps |= UFS_MTK_CAP_RTFF_MTCMOS; in ufs_mtk_init_host_caps()
719 if (of_property_read_bool(np, "mediatek,ufs-broken-rtc")) in ufs_mtk_init_host_caps()
720 host->caps |= UFS_MTK_CAP_MCQ_BROKEN_RTC; in ufs_mtk_init_host_caps()
722 dev_info(hba->dev, "caps: 0x%x", host->caps); in ufs_mtk_init_host_caps()
735 phy_power_on(host->mphy); in ufs_mtk_pwr_ctrl()
743 phy_power_off(host->mphy); in ufs_mtk_pwr_ctrl()
752 if (!hba->mcq_enabled) in ufs_mtk_mcq_disable_irq()
755 if (host->mcq_nr_intr == 0) in ufs_mtk_mcq_disable_irq()
758 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_mcq_disable_irq()
759 irq = host->mcq_intr_info[i].irq; in ufs_mtk_mcq_disable_irq()
762 host->is_mcq_intr_enabled = false; in ufs_mtk_mcq_disable_irq()
770 if (!hba->mcq_enabled) in ufs_mtk_mcq_enable_irq()
773 if (host->mcq_nr_intr == 0) in ufs_mtk_mcq_enable_irq()
776 if (host->is_mcq_intr_enabled == true) in ufs_mtk_mcq_enable_irq()
779 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_mcq_enable_irq()
780 irq = host->mcq_intr_info[i].irq; in ufs_mtk_mcq_enable_irq()
783 host->is_mcq_intr_enabled = true; in ufs_mtk_mcq_enable_irq()
787 * ufs_mtk_setup_clocks - enables/disable clocks
792 * Return: 0 on success, non-zero on failure.
816 * Gate ref-clk and poweroff mphy if link state is in in ufs_mtk_setup_clocks()
817 * OFF or Hibern8 by either Auto-Hibern8 or in ufs_mtk_setup_clocks()
830 dev_warn(hba->dev, "Clock is not turned off, hba->ahit = 0x%x, AHIT = 0x%x\n", in ufs_mtk_setup_clocks()
831 hba->ahit, in ufs_mtk_setup_clocks()
844 static u32 ufs_mtk_mcq_get_irq(struct ufs_hba *hba, unsigned int cpu) in ufs_mtk_mcq_get_irq() argument
847 struct blk_mq_tag_set *tag_set = &hba->host->tag_set; in ufs_mtk_mcq_get_irq()
848 struct blk_mq_queue_map *map = &tag_set->map[HCTX_TYPE_DEFAULT]; in ufs_mtk_mcq_get_irq()
849 unsigned int nr = map->nr_queues; in ufs_mtk_mcq_get_irq()
852 q_index = map->mq_map[cpu]; in ufs_mtk_mcq_get_irq()
854 dev_err(hba->dev, "hwq index %d exceed %d\n", in ufs_mtk_mcq_get_irq()
859 return host->mcq_intr_info[q_index].irq; in ufs_mtk_mcq_get_irq()
862 static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu) in ufs_mtk_mcq_set_irq_affinity() argument
867 irq = ufs_mtk_mcq_get_irq(hba, cpu); in ufs_mtk_mcq_set_irq_affinity()
869 dev_err(hba->dev, "invalid irq. unable to bind irq to cpu%d", cpu); in ufs_mtk_mcq_set_irq_affinity()
874 _cpu = (cpu == 0) ? 3 : cpu; in ufs_mtk_mcq_set_irq_affinity()
877 dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n", in ufs_mtk_mcq_set_irq_affinity()
881 dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu); in ufs_mtk_mcq_set_irq_affinity()
897 dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver, is_legacy); in ufs_mtk_is_legacy_chipset()
924 host->ip_ver = hw_ip_ver; in ufs_mtk_get_hw_ip_version()
926 host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(hba, hw_ip_ver); in ufs_mtk_get_hw_ip_version()
934 if (host->hw_ver.major) in ufs_mtk_get_controller_version()
938 host->hw_ver.major = 2; in ufs_mtk_get_controller_version()
943 host->hw_ver.major = 3; in ufs_mtk_get_controller_version()
948 if (hba->ufs_version < ufshci_version(3, 0)) in ufs_mtk_get_controller_version()
949 hba->ufs_version = ufshci_version(3, 0); in ufs_mtk_get_controller_version()
956 return hba->ufs_version; in ufs_mtk_get_ufs_hci_version()
960 * ufs_mtk_init_clocks - Init mtk driver private clocks
967 struct list_head *head = &hba->clk_list_head; in ufs_mtk_init_clocks()
969 struct device *dev = hba->dev; in ufs_mtk_init_clocks()
979 if (!strcmp(clki->name, "ufs_sel")) { in ufs_mtk_init_clocks()
980 host->mclk.ufs_sel_clki = clki; in ufs_mtk_init_clocks()
981 } else if (!strcmp(clki->name, "ufs_sel_max_src")) { in ufs_mtk_init_clocks()
982 host->mclk.ufs_sel_max_clki = clki; in ufs_mtk_init_clocks()
983 clk_disable_unprepare(clki->clk); in ufs_mtk_init_clocks()
984 list_del(&clki->list); in ufs_mtk_init_clocks()
985 } else if (!strcmp(clki->name, "ufs_sel_min_src")) { in ufs_mtk_init_clocks()
986 host->mclk.ufs_sel_min_clki = clki; in ufs_mtk_init_clocks()
987 clk_disable_unprepare(clki->clk); in ufs_mtk_init_clocks()
988 list_del(&clki->list); in ufs_mtk_init_clocks()
989 } else if (!strcmp(clki->name, "ufs_fde")) { in ufs_mtk_init_clocks()
990 host->mclk.ufs_fde_clki = clki; in ufs_mtk_init_clocks()
991 } else if (!strcmp(clki->name, "ufs_fde_max_src")) { in ufs_mtk_init_clocks()
992 host->mclk.ufs_fde_max_clki = clki; in ufs_mtk_init_clocks()
993 clk_disable_unprepare(clki->clk); in ufs_mtk_init_clocks()
994 list_del(&clki->list); in ufs_mtk_init_clocks()
995 } else if (!strcmp(clki->name, "ufs_fde_min_src")) { in ufs_mtk_init_clocks()
996 host->mclk.ufs_fde_min_clki = clki; in ufs_mtk_init_clocks()
997 clk_disable_unprepare(clki->clk); in ufs_mtk_init_clocks()
998 list_del(&clki->list); in ufs_mtk_init_clocks()
1003 dev_info(hba->dev, "clk \"%s\" present", clki->name); in ufs_mtk_init_clocks()
1007 hba->caps &= ~UFSHCD_CAP_CLK_SCALING; in ufs_mtk_init_clocks()
1008 dev_info(hba->dev, in ufs_mtk_init_clocks()
1009 "%s: Clk-scaling not ready. Feature disabled.", in ufs_mtk_init_clocks()
1018 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore"); in ufs_mtk_init_clocks()
1020 dev_info(dev, "failed to get dvfsrc-vcore: %ld", in ufs_mtk_init_clocks()
1025 if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min", in ufs_mtk_init_clocks()
1027 dev_info(dev, "failed to get clk-scale-up-vcore-min"); in ufs_mtk_init_clocks()
1031 host->mclk.reg_vcore = reg; in ufs_mtk_init_clocks()
1032 host->mclk.vcore_volt = volt; in ufs_mtk_init_clocks()
1035 if (reg && volt && host->clk_scale_up) { in ufs_mtk_init_clocks()
1037 dev_info(hba->dev, in ufs_mtk_init_clocks()
1046 struct ufs_vreg_info *info = &hba->vreg_info; in ufs_mtk_vreg_fix_vcc()
1047 struct device_node *np = hba->dev->of_node; in ufs_mtk_vreg_fix_vcc()
1048 struct device *dev = hba->dev; in ufs_mtk_vreg_fix_vcc()
1053 if (info->vcc) in ufs_mtk_vreg_fix_vcc()
1056 if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) { in ufs_mtk_vreg_fix_vcc()
1059 snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1); in ufs_mtk_vreg_fix_vcc()
1061 return -ENODEV; in ufs_mtk_vreg_fix_vcc()
1062 } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) { in ufs_mtk_vreg_fix_vcc()
1063 ver = (hba->dev_info.wspecversion & 0xF00) >> 8; in ufs_mtk_vreg_fix_vcc()
1064 snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver); in ufs_mtk_vreg_fix_vcc()
1069 err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false); in ufs_mtk_vreg_fix_vcc()
1073 err = ufshcd_get_vreg(dev, info->vcc); in ufs_mtk_vreg_fix_vcc()
1077 err = regulator_enable(info->vcc->reg); in ufs_mtk_vreg_fix_vcc()
1079 info->vcc->enabled = true; in ufs_mtk_vreg_fix_vcc()
1088 struct ufs_vreg_info *info = &hba->vreg_info; in ufs_mtk_vreg_fix_vccqx()
1091 if (hba->dev_info.wspecversion >= 0x0300) { in ufs_mtk_vreg_fix_vccqx()
1092 vreg_on = &info->vccq; in ufs_mtk_vreg_fix_vccqx()
1093 vreg_off = &info->vccq2; in ufs_mtk_vreg_fix_vccqx()
1095 vreg_on = &info->vccq2; in ufs_mtk_vreg_fix_vccqx()
1096 vreg_off = &info->vccq; in ufs_mtk_vreg_fix_vccqx()
1100 (*vreg_on)->always_on = true; in ufs_mtk_vreg_fix_vccqx()
1103 regulator_disable((*vreg_off)->reg); in ufs_mtk_vreg_fix_vccqx()
1104 devm_kfree(hba->dev, (*vreg_off)->name); in ufs_mtk_vreg_fix_vccqx()
1105 devm_kfree(hba->dev, *vreg_off); in ufs_mtk_vreg_fix_vccqx()
1118 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) { in ufs_mtk_setup_clk_gating()
1120 hba->ahit); in ufs_mtk_setup_clk_gating()
1122 hba->ahit); in ufs_mtk_setup_clk_gating()
1127 spin_lock_irqsave(hba->host->host_lock, flags); in ufs_mtk_setup_clk_gating()
1128 hba->clk_gating.delay_ms = max(ah_ms, 10U); in ufs_mtk_setup_clk_gating()
1129 spin_unlock_irqrestore(hba->host->host_lock, flags); in ufs_mtk_setup_clk_gating()
1138 switch (hba->dev_info.wmanufacturerid) { in ufs_mtk_fix_ahit()
1140 /* configure auto-hibern8 timer to 3.5 ms */ in ufs_mtk_fix_ahit()
1145 /* configure auto-hibern8 timer to 2 ms */ in ufs_mtk_fix_ahit()
1150 /* configure auto-hibern8 timer to 1 ms */ in ufs_mtk_fix_ahit()
1155 hba->ahit = ufshcd_us_to_ahit(us); in ufs_mtk_fix_ahit()
1163 /* UFS version is below 4.0, clock scaling is not necessary */ in ufs_mtk_fix_clock_scaling()
1164 if ((hba->dev_info.wspecversion < 0x0400) && in ufs_mtk_fix_clock_scaling()
1166 hba->caps &= ~UFSHCD_CAP_CLK_SCALING; in ufs_mtk_fix_clock_scaling()
1179 host->mcq_nr_intr = UFSHCD_MAX_Q_NR; in ufs_mtk_init_mcq_irq()
1180 pdev = container_of(hba->dev, struct platform_device, dev); in ufs_mtk_init_mcq_irq()
1182 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ) in ufs_mtk_init_mcq_irq()
1185 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_init_mcq_irq()
1189 host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ; in ufs_mtk_init_mcq_irq()
1192 host->mcq_intr_info[i].hba = hba; in ufs_mtk_init_mcq_irq()
1193 host->mcq_intr_info[i].irq = irq; in ufs_mtk_init_mcq_irq()
1194 dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq); in ufs_mtk_init_mcq_irq()
1200 for (i = 0; i < host->mcq_nr_intr; i++) in ufs_mtk_init_mcq_irq()
1201 host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ; in ufs_mtk_init_mcq_irq()
1203 host->mcq_nr_intr = 0; in ufs_mtk_init_mcq_irq()
1207 * ufs_mtk_init - find other essential mmio bases
1213 * Return: -EPROBE_DEFER if binding fails, returns negative error
1219 struct device *dev = hba->dev; in ufs_mtk_init()
1221 struct Scsi_Host *shost = hba->host; in ufs_mtk_init()
1227 err = -ENOMEM; in ufs_mtk_init()
1228 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__); in ufs_mtk_init()
1232 host->hba = hba; in ufs_mtk_init()
1237 err = -EINVAL; in ufs_mtk_init()
1253 if (host->mphy_reset) in ufs_mtk_init()
1257 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_mtk_init()
1259 /* Enable clock-gating */ in ufs_mtk_init()
1260 hba->caps |= UFSHCD_CAP_CLK_GATING; in ufs_mtk_init()
1263 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_mtk_init()
1266 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_mtk_init()
1269 hba->caps |= UFSHCD_CAP_CLK_SCALING; in ufs_mtk_init()
1270 host->clk_scale_up = true; /* default is max freq */ in ufs_mtk_init()
1273 shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS; in ufs_mtk_init()
1275 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL; in ufs_mtk_init()
1277 hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR; in ufs_mtk_init()
1278 if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC) in ufs_mtk_init()
1279 hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC; in ufs_mtk_init()
1281 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80); in ufs_mtk_init()
1283 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) in ufs_mtk_init()
1284 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_mtk_init()
1286 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ) in ufs_mtk_init()
1287 hba->quirks |= UFSHCD_QUIRK_BROKEN_LSDBS_CAP; in ufs_mtk_init()
1326 if (dev_req_params->hs_rate == hba->pwr_info.hs_rate) in ufs_mtk_pmc_via_fastauto()
1329 if (dev_req_params->pwr_tx != FAST_MODE && in ufs_mtk_pmc_via_fastauto()
1330 dev_req_params->gear_tx < UFS_HS_G4) in ufs_mtk_pmc_via_fastauto()
1333 if (dev_req_params->pwr_rx != FAST_MODE && in ufs_mtk_pmc_via_fastauto()
1334 dev_req_params->gear_rx < UFS_HS_G4) in ufs_mtk_pmc_via_fastauto()
1337 if (dev_req_params->pwr_tx == SLOW_MODE || in ufs_mtk_pmc_via_fastauto()
1338 dev_req_params->pwr_rx == SLOW_MODE) in ufs_mtk_pmc_via_fastauto()
1386 if (dev_max_params->pwr_rx == SLOW_MODE || in ufs_mtk_pre_pwr_change()
1387 dev_max_params->pwr_tx == SLOW_MODE) in ufs_mtk_pre_pwr_change()
1406 dev_req_params->lane_tx); in ufs_mtk_pre_pwr_change()
1408 dev_req_params->lane_rx); in ufs_mtk_pre_pwr_change()
1410 dev_req_params->hs_rate); in ufs_mtk_pre_pwr_change()
1415 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { in ufs_mtk_pre_pwr_change()
1441 dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n", in ufs_mtk_pre_pwr_change()
1447 if (dev_req_params->gear_rx == hba->pwr_info.gear_rx && in ufs_mtk_pre_pwr_change()
1448 dev_req_params->gear_tx == hba->pwr_info.gear_tx && in ufs_mtk_pre_pwr_change()
1449 dev_req_params->lane_rx == hba->pwr_info.lane_rx && in ufs_mtk_pre_pwr_change()
1450 dev_req_params->lane_tx == hba->pwr_info.lane_tx && in ufs_mtk_pre_pwr_change()
1451 dev_req_params->pwr_rx == hba->pwr_info.pwr_rx && in ufs_mtk_pre_pwr_change()
1452 dev_req_params->pwr_tx == hba->pwr_info.pwr_tx && in ufs_mtk_pre_pwr_change()
1453 dev_req_params->hs_rate == hba->pwr_info.hs_rate) { in ufs_mtk_pre_pwr_change()
1457 if (dev_req_params->pwr_rx == FAST_MODE || in ufs_mtk_pre_pwr_change()
1458 dev_req_params->pwr_rx == FASTAUTO_MODE) { in ufs_mtk_pre_pwr_change()
1459 if (host->hw_ver.major >= 3) { in ufs_mtk_pre_pwr_change()
1461 dev_req_params->gear_tx, in ufs_mtk_pre_pwr_change()
1465 dev_req_params->gear_tx, in ufs_mtk_pre_pwr_change()
1470 dev_req_params->gear_tx, in ufs_mtk_pre_pwr_change()
1481 /* disable auto-hibern8 */ in ufs_mtk_auto_hibern8_disable()
1484 /* wait host return to idle state when auto-hibern8 off */ in ufs_mtk_auto_hibern8_disable()
1493 dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret); in ufs_mtk_auto_hibern8_disable()
1498 ret = -EBUSY; in ufs_mtk_auto_hibern8_disable()
1526 ret = -EINVAL; in ufs_mtk_pwr_change_notify()
1543 * Forcibly set as non-LPM mode if UIC commands is failed in ufs_mtk_unipro_set_lpm()
1544 * to use default hba_enable_delay_us value for re-enabling in ufs_mtk_unipro_set_lpm()
1547 host->unipro_lpm = lpm; in ufs_mtk_unipro_set_lpm()
1584 if (host->ip_ver == IP_VER_MT6989) { in ufs_mtk_pre_link()
1602 if (host->ip_ver >= IP_VER_MT6899) { in ufs_mtk_post_link()
1625 ret = -EINVAL; in ufs_mtk_link_startup_notify()
1642 * The reset signal is active low. UFS devices shall detect in ufs_mtk_device_reset()
1655 dev_info(hba->dev, "device reset done\n"); in ufs_mtk_device_reset()
1672 if (host->ip_ver < IP_VER_MT6899) { in ufs_mtk_link_set_hpm()
1691 dev_warn(hba->dev, "wait idle fail, err=%d\n", err); in ufs_mtk_link_set_hpm()
1696 dev_warn(hba->dev, "exit h8 state fail, err=%d\n", err); in ufs_mtk_link_set_hpm()
1705 if (hba->mcq_enabled) { in ufs_mtk_link_set_hpm()
1708 ufshcd_mcq_config_mac(hba, hba->nutrs); in ufs_mtk_link_set_hpm()
1738 if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2) in ufs_mtk_vccqx_set_lpm()
1741 if (hba->vreg_info.vccq) in ufs_mtk_vccqx_set_lpm()
1742 vccqx = hba->vreg_info.vccq; in ufs_mtk_vccqx_set_lpm()
1744 vccqx = hba->vreg_info.vccq2; in ufs_mtk_vccqx_set_lpm()
1746 regulator_set_mode(vccqx->reg, in ufs_mtk_vccqx_set_lpm()
1755 (unsigned long)hba->dev_info.wspecversion, in ufs_mtk_vsx_set_lpm()
1768 if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2) in ufs_mtk_dev_vreg_set_lpm()
1771 /* VCC is always-on, control vsx only */ in ufs_mtk_dev_vreg_set_lpm()
1772 if (!hba->vreg_info.vcc) in ufs_mtk_dev_vreg_set_lpm()
1776 if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) { in ufs_mtk_dev_vreg_set_lpm()
1817 * ufshcd_suspend() re-enabling regulators while vreg is still in ufs_mtk_suspend()
1818 * in low-power mode. in ufs_mtk_suspend()
1830 /* Release pm_qos/clk if in scale-up mode during suspend */ in ufs_mtk_suspend()
1831 if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { in ufs_mtk_suspend()
1835 hba->pwr_info.gear_rx >= UFS_HS_G5)) { in ufs_mtk_suspend()
1847 return -EAGAIN; in ufs_mtk_suspend()
1856 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) in ufs_mtk_resume()
1865 /* Request pm_qos/clk if in scale-up mode after resume */ in ufs_mtk_resume()
1866 if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { in ufs_mtk_resume()
1870 hba->pwr_info.gear_rx >= UFS_HS_G5)) { in ufs_mtk_resume()
1889 dev_err(hba->dev, "Device PM: req=%d, status:%d, err:%d\n", in ufs_mtk_resume()
1890 hba->dev->power.request, in ufs_mtk_resume()
1891 hba->dev->power.runtime_status, in ufs_mtk_resume()
1892 hba->dev->power.runtime_error); in ufs_mtk_resume()
1908 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4, in ufs_mtk_dbg_register_dump()
1918 struct ufs_dev_info *dev_info = &hba->dev_info; in ufs_mtk_apply_dev_quirks()
1919 u16 mid = dev_info->wmanufacturerid; in ufs_mtk_apply_dev_quirks()
1920 unsigned int cpu; in ufs_mtk_apply_dev_quirks() local
1922 if (hba->mcq_enabled) { in ufs_mtk_apply_dev_quirks()
1924 for (cpu = 0; cpu < nr_cpu_ids; cpu++) in ufs_mtk_apply_dev_quirks()
1925 ufs_mtk_mcq_set_irq_affinity(hba, cpu); in ufs_mtk_apply_dev_quirks()
1934 (STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1935 STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1936 STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1937 STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1938 STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) || in ufs_mtk_apply_dev_quirks()
1939 STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) { in ufs_mtk_apply_dev_quirks()
1965 if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc) { in ufs_mtk_fixup_dev_quirks()
1966 hba->vreg_info.vcc->always_on = true; in ufs_mtk_fixup_dev_quirks()
1968 * VCC will be kept always-on thus we don't in ufs_mtk_fixup_dev_quirks()
1971 hba->dev_quirks &= ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM; in ufs_mtk_fixup_dev_quirks()
1991 dev_info(hba->dev, in ufs_mtk_event_notify()
1999 dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); in ufs_mtk_event_notify()
2004 dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); in ufs_mtk_event_notify()
2013 hba->clk_scaling.min_gear = UFS_HS_G4; in ufs_mtk_config_scaling_param()
2015 hba->vps->devfreq_profile.polling_ms = 200; in ufs_mtk_config_scaling_param()
2016 hba->vps->ondemand_data.upthreshold = 50; in ufs_mtk_config_scaling_param()
2017 hba->vps->ondemand_data.downdifferential = 20; in ufs_mtk_config_scaling_param()
2023 struct ufs_mtk_clk *mclk = &host->mclk; in _ufs_mtk_clk_scale()
2024 struct ufs_clk_info *clki = mclk->ufs_sel_clki; in _ufs_mtk_clk_scale()
2025 struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki; in _ufs_mtk_clk_scale()
2031 if (!hba->clk_scaling.is_initialized) in _ufs_mtk_clk_scale()
2037 reg = host->mclk.reg_vcore; in _ufs_mtk_clk_scale()
2038 volt = host->mclk.vcore_volt; in _ufs_mtk_clk_scale()
2042 if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) in _ufs_mtk_clk_scale()
2045 ret = clk_prepare_enable(clki->clk); in _ufs_mtk_clk_scale()
2047 dev_info(hba->dev, in _ufs_mtk_clk_scale()
2053 ret = clk_prepare_enable(fde_clki->clk); in _ufs_mtk_clk_scale()
2055 dev_info(hba->dev, in _ufs_mtk_clk_scale()
2065 dev_info(hba->dev, in _ufs_mtk_clk_scale()
2071 ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); in _ufs_mtk_clk_scale()
2073 dev_info(hba->dev, "Failed to set clk mux, ret = %d\n", in _ufs_mtk_clk_scale()
2078 ret = clk_set_parent(fde_clki->clk, in _ufs_mtk_clk_scale()
2079 mclk->ufs_fde_max_clki->clk); in _ufs_mtk_clk_scale()
2081 dev_info(hba->dev, in _ufs_mtk_clk_scale()
2088 ret = clk_set_parent(fde_clki->clk, in _ufs_mtk_clk_scale()
2089 mclk->ufs_fde_min_clki->clk); in _ufs_mtk_clk_scale()
2091 dev_info(hba->dev, in _ufs_mtk_clk_scale()
2098 ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk); in _ufs_mtk_clk_scale()
2100 dev_info(hba->dev, "Failed to set clk mux, ret = %d\n", in _ufs_mtk_clk_scale()
2108 dev_info(hba->dev, in _ufs_mtk_clk_scale()
2115 clk_disable_unprepare(clki->clk); in _ufs_mtk_clk_scale()
2118 clk_disable_unprepare(fde_clki->clk); in _ufs_mtk_clk_scale()
2122 * ufs_mtk_clk_scale - Internal clk scaling operation
2125 * The ufs_sel downstream to ufs_ck which feeds directly to UFS hardware.
2136 struct ufs_mtk_clk *mclk = &host->mclk; in ufs_mtk_clk_scale()
2137 struct ufs_clk_info *clki = mclk->ufs_sel_clki; in ufs_mtk_clk_scale()
2139 if (host->clk_scale_up == scale_up) in ufs_mtk_clk_scale()
2147 host->clk_scale_up = scale_up; in ufs_mtk_clk_scale()
2151 clki->curr_freq = clki->max_freq; in ufs_mtk_clk_scale()
2153 clki->curr_freq = clki->min_freq; in ufs_mtk_clk_scale()
2155 trace_ufs_mtk_clk_scale(clki->name, scale_up, clk_get_rate(clki->clk)); in ufs_mtk_clk_scale()
2181 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ) in ufs_mtk_get_hba_mac()
2182 return -EPERM; in ufs_mtk_get_hba_mac()
2192 hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD; in ufs_mtk_op_runtime_config()
2193 hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS; in ufs_mtk_op_runtime_config()
2194 hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD; in ufs_mtk_op_runtime_config()
2195 hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS; in ufs_mtk_op_runtime_config()
2198 opr = &hba->mcq_opr[i]; in ufs_mtk_op_runtime_config()
2199 opr->stride = REG_UFS_MCQ_STRIDE; in ufs_mtk_op_runtime_config()
2200 opr->base = hba->mmio_base + opr->offset; in ufs_mtk_op_runtime_config()
2211 if (!host->mcq_nr_intr) { in ufs_mtk_mcq_config_resource()
2212 dev_info(hba->dev, "IRQs not ready. MCQ disabled."); in ufs_mtk_mcq_config_resource()
2213 return -EINVAL; in ufs_mtk_mcq_config_resource()
2216 hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities); in ufs_mtk_mcq_config_resource()
2223 struct ufs_hba *hba = mcq_intr_info->hba; in ufs_mtk_mcq_intr()
2226 int qid = mcq_intr_info->qid; in ufs_mtk_mcq_intr()
2228 hwq = &hba->uhq[qid]; in ufs_mtk_mcq_intr()
2246 for (i = 0; i < host->mcq_nr_intr; i++) { in ufs_mtk_config_mcq_irq()
2247 irq = host->mcq_intr_info[i].irq; in ufs_mtk_config_mcq_irq()
2249 dev_err(hba->dev, "invalid irq. %d\n", i); in ufs_mtk_config_mcq_irq()
2250 return -ENOPARAM; in ufs_mtk_config_mcq_irq()
2253 host->mcq_intr_info[i].qid = i; in ufs_mtk_config_mcq_irq()
2254 ret = devm_request_irq(hba->dev, irq, ufs_mtk_mcq_intr, 0, UFSHCD, in ufs_mtk_config_mcq_irq()
2255 &host->mcq_intr_info[i]); in ufs_mtk_config_mcq_irq()
2257 dev_dbg(hba->dev, "request irq %d intr %s\n", irq, ret ? "failed" : ""); in ufs_mtk_config_mcq_irq()
2260 dev_err(hba->dev, "Cannot request irq %d\n", ret); in ufs_mtk_config_mcq_irq()
2264 host->is_mcq_intr_enabled = true; in ufs_mtk_config_mcq_irq()
2274 if (!host->mcq_set_intr) { in ufs_mtk_config_mcq()
2284 host->mcq_set_intr = true; in ufs_mtk_config_mcq()
2300 struct ufs_hba *hba = shost_priv(sdev->host); in ufs_mtk_config_scsi_dev()
2302 dev_dbg(hba->dev, "lu %llu scsi device configured", sdev->lun); in ufs_mtk_config_scsi_dev()
2303 if (sdev->lun == 2) in ufs_mtk_config_scsi_dev()
2304 blk_queue_flag_set(QUEUE_FLAG_SAME_FORCE, sdev->request_queue); in ufs_mtk_config_scsi_dev()
2308 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
2340 * ufs_mtk_probe - probe routine of the driver
2343 * Return: zero for success and non-zero for failure.
2348 struct device *dev = &pdev->dev, *phy_dev = NULL; in ufs_mtk_probe()
2356 "ti,syscon-reset"); in ufs_mtk_probe()
2358 dev_notice(dev, "find ti,syscon-reset fail\n"); in ufs_mtk_probe()
2366 link = device_link_add(dev, &reset_pdev->dev, in ufs_mtk_probe()
2368 put_device(&reset_pdev->dev); in ufs_mtk_probe()
2374 if (link->status == DL_STATE_DORMANT) { in ufs_mtk_probe()
2375 err = -EPROBE_DEFER; in ufs_mtk_probe()
2381 phy_node = of_parse_phandle(dev->of_node, "phys", 0); in ufs_mtk_probe()
2387 phy_dev = &phy_pdev->dev; in ufs_mtk_probe()
2413 host->phy_dev = phy_dev; in ufs_mtk_probe()
2430 * ufs_mtk_remove - set driver_data of the device to NULL
2447 if (hba->shutting_down) { in ufs_mtk_system_suspend()
2448 ret = -EBUSY; in ufs_mtk_system_suspend()
2456 if (pm_runtime_suspended(hba->dev)) in ufs_mtk_system_suspend()
2474 if (pm_runtime_suspended(hba->dev)) in ufs_mtk_system_resume()
2506 if (host->phy_dev) in ufs_mtk_runtime_suspend()
2507 pm_runtime_put_sync(host->phy_dev); in ufs_mtk_runtime_suspend()
2521 if (host->phy_dev) in ufs_mtk_runtime_resume()
2522 pm_runtime_get_sync(host->phy_dev); in ufs_mtk_runtime_resume()
2543 .name = "ufshcd-mtk",
2551 MODULE_DESCRIPTION("MediaTek UFS Host Driver");