Lines Matching refs:ufs
24 #include <ufs/ufshcd.h>
26 #include <ufs/ufshci.h>
27 #include <ufs/unipro.h>
29 #include "ufs-exynos.h"
176 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
177 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
179 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
181 exynos_ufs_auto_ctrl_hcc(ufs, true);
184 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
186 exynos_ufs_auto_ctrl_hcc(ufs, false);
190 struct exynos_ufs *ufs, u32 *val)
192 *val = hci_readl(ufs, HCI_MISC);
193 exynos_ufs_auto_ctrl_hcc(ufs, false);
197 struct exynos_ufs *ufs, u32 *val)
199 hci_writel(ufs, *val, HCI_MISC);
202 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
204 exynos_ufs_ctrl_clkstop(ufs, true);
207 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
209 exynos_ufs_ctrl_clkstop(ufs, false);
212 static int exynos_ufs_shareability(struct exynos_ufs *ufs)
215 if (ufs->sysreg) {
216 return regmap_update_bits(ufs->sysreg,
217 ufs->iocc_offset,
218 ufs->iocc_mask, ufs->iocc_val);
224 static int gs101_ufs_drv_init(struct exynos_ufs *ufs)
226 struct ufs_hba *hba = ufs->hba;
236 reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE);
237 hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE);
239 return exynos_ufs_shareability(ufs);
242 static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs)
244 return exynos_ufs_shareability(ufs);
247 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
249 struct ufs_hba *hba = ufs->hba;
254 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH);
256 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
261 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
263 struct ufs_hba *hba = ufs->hba;
267 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
268 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
271 for_each_ufs_rx_lane(ufs, i) {
273 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
288 for_each_ufs_tx_lane(ufs, i) {
290 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
315 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
318 struct ufs_hba *hba = ufs->hba;
328 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
331 struct ufs_hba *hba = ufs->hba;
342 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
344 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
346 struct ufs_hba *hba = ufs->hba;
350 for_each_ufs_tx_lane(ufs, i)
352 for_each_ufs_rx_lane(ufs, i) {
358 for_each_ufs_tx_lane(ufs, i)
374 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
376 struct ufs_hba *hba = ufs->hba;
380 for_each_ufs_tx_lane(ufs, i) {
384 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
395 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
398 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
403 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
406 struct ufs_hba *hba = ufs->hba;
426 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
428 u32 misc = hci_readl(ufs, HCI_MISC);
431 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
433 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
436 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
438 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
439 u32 misc = hci_readl(ufs, HCI_MISC);
442 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
443 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
445 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
446 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
450 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
452 struct ufs_hba *hba = ufs->hba;
466 ufs->clk_hci_core = clki->clk;
468 ufs->clk_unipro_main = clki->clk;
472 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
478 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
479 pclk_rate = clk_get_rate(ufs->clk_hci_core);
480 f_min = ufs->pclk_avail_min;
481 f_max = ufs->pclk_avail_max;
483 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
499 ufs->pclk_rate = pclk_rate;
500 ufs->pclk_div = div;
506 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
508 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
511 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
512 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
517 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
519 struct ufs_hba *hba = ufs->hba;
520 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
526 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
528 struct ufs_hba *hba = ufs->hba;
529 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
537 clk_period = UNIPRO_PCLK_PERIOD(ufs);
557 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
560 long pclk_rate = ufs->pclk_rate;
563 clk_period = UNIPRO_PCLK_PERIOD(ufs);
569 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
571 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
572 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
574 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)
578 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
580 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
582 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
584 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
586 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
588 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
591 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
593 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
595 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
597 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
599 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
601 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
604 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
606 struct ufs_hba *hba = ufs->hba;
607 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
610 exynos_ufs_set_pwm_clk_div(ufs);
614 for_each_ufs_rx_lane(ufs, i) {
616 ufs->drv_data->uic_attr->rx_filler_enable);
633 for_each_ufs_tx_lane(ufs, i) {
652 ufs->drv_data->uic_attr->tx_min_activatetime);
658 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
660 struct ufs_hba *hba = ufs->hba;
661 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
666 for_each_ufs_rx_lane(ufs, i) {
688 for_each_ufs_rx_lane(ufs, i) {
704 for_each_ufs_rx_lane(ufs, i) {
728 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
730 struct ufs_hba *hba = ufs->hba;
751 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
755 if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)
758 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
761 reg = ufsp_readl(ufs, UFSPRSECURITY);
762 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
763 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
764 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
765 ufsp_writel(ufs, 0xff, UFSPSLUN0);
766 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
768 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
771 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
774 struct ufs_hba *hba = ufs->hba;
793 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
798 for_each_ufs_rx_lane(ufs, i)
824 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
825 struct phy *generic_phy = ufs->phy;
847 if (ufs->drv_data->pre_pwr_change)
848 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
851 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
875 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
876 struct phy *generic_phy = ufs->phy;
888 if (ufs->drv_data->post_pwr_change)
889 ufs->drv_data->post_pwr_change(ufs, pwr_req);
915 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
918 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
921 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
923 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
929 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
932 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
937 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
943 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
948 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
950 struct ufs_hba *hba = ufs->hba;
951 struct phy *generic_phy = ufs->phy;
954 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
956 &ufs->avail_ln_rx);
958 &ufs->avail_ln_tx);
959 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
961 ufs->avail_ln_rx, ufs->avail_ln_tx);
964 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
990 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
992 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
993 struct ufs_hba *hba = ufs->hba;
997 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1000 ufs->drv_data->uic_attr->tx_trailingclks);
1011 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
1015 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
1018 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
1021 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
1024 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
1027 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
1035 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1037 if (!ufs)
1041 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1042 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1043 exynos_ufs_ungate_clks(ufs);
1045 exynos_ufs_gate_clks(ufs);
1046 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1047 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1055 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1058 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
1059 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
1060 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
1061 exynos_ufs_set_unipro_pclk_div(ufs);
1066 exynos_ufs_config_unipro(ufs);
1068 if (ufs->drv_data->pre_link)
1069 ufs->drv_data->pre_link(ufs);
1072 exynos_ufs_phy_init(ufs);
1073 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
1074 exynos_ufs_config_phy_time_attr(ufs);
1075 exynos_ufs_config_phy_cap_attr(ufs);
1081 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
1086 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) {
1087 val = hci_readl(ufs, HCI_V2P1_CTRL);
1089 hci_writel(ufs, val, HCI_V2P1_CTRL);
1092 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
1093 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
1098 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1099 struct phy *generic_phy = ufs->phy;
1100 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1103 exynos_ufs_establish_connt(ufs);
1104 exynos_ufs_fit_aggr_timeout(ufs);
1106 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
1110 hci_writel(ufs, val, HCI_TXPRDT_ENTRY_SIZE);
1112 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE);
1113 hci_writel(ufs, BIT(hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
1114 hci_writel(ufs, BIT(hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
1115 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
1117 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
1131 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
1136 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1160 if (ufs->drv_data->post_link)
1161 ufs->drv_data->post_link(ufs);
1166 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
1172 ufs->drv_data = device_get_match_data(dev);
1174 if (ufs->drv_data && ufs->drv_data->uic_attr) {
1175 attr = ufs->drv_data->uic_attr;
1182 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");
1183 if (IS_ERR(ufs->sysreg))
1184 ufs->sysreg = NULL;
1187 &ufs->iocc_offset)) {
1189 ufs->iocc_offset = UFS_SHAREABILITY_OFFSET;
1193 ufs->iocc_mask = ufs->drv_data->iocc_mask;
1199 ufs->iocc_val = ufs->iocc_mask;
1201 ufs->iocc_val = 0;
1203 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
1204 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
1218 struct exynos_ufs *ufs)
1220 ufs->hba = hba;
1221 ufs->opts = ufs->drv_data->opts;
1222 ufs->rx_sel_idx = PA_MAXDATALANES;
1223 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
1224 ufs->rx_sel_idx = 0;
1225 hba->priv = (void *)ufs;
1226 hba->quirks = ufs->drv_data->quirks;
1283 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs)
1310 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
1442 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs)
1458 struct exynos_ufs *ufs;
1461 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1462 if (!ufs)
1466 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1467 if (IS_ERR(ufs->reg_hci)) {
1469 return PTR_ERR(ufs->reg_hci);
1473 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
1474 if (IS_ERR(ufs->reg_unipro)) {
1476 return PTR_ERR(ufs->reg_unipro);
1479 /* ufs protector */
1480 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
1481 if (IS_ERR(ufs->reg_ufsp)) {
1482 dev_err(dev, "cannot ioremap for ufs protector register\n");
1483 return PTR_ERR(ufs->reg_ufsp);
1486 ret = exynos_ufs_parse_dt(dev, ufs);
1492 ufs->phy = devm_phy_get(dev, "ufs-phy");
1493 if (IS_ERR(ufs->phy)) {
1494 ret = PTR_ERR(ufs->phy);
1495 dev_err(dev, "failed to get ufs-phy\n");
1499 exynos_ufs_priv_init(hba, ufs);
1501 exynos_ufs_fmp_init(hba, ufs);
1503 if (ufs->drv_data->drv_init) {
1504 ret = ufs->drv_data->drv_init(ufs);
1511 ret = exynos_ufs_get_clk_info(ufs);
1514 exynos_ufs_specify_phy_time_attr(ufs);
1516 exynos_ufs_config_smu(ufs);
1528 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1530 phy_power_off(ufs->phy);
1531 phy_exit(ufs->phy);
1536 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1541 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1543 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1546 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1554 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1560 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1562 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1564 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1569 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1570 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1573 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1574 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1575 exynos_ufs_ungate_clks(ufs);
1577 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1588 ufs->entry_hibern8_t);
1602 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1605 ufs->entry_hibern8_t = ktime_get();
1606 exynos_ufs_gate_clks(ufs);
1607 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1608 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1615 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1628 if (ufs->drv_data->pre_hce_enable) {
1629 ret = ufs->drv_data->pre_hce_enable(ufs);
1640 exynos_ufs_calc_pwm_clk_div(ufs);
1641 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1642 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1644 if (ufs->drv_data->post_hce_enable)
1645 ret = ufs->drv_data->post_hce_enable(ufs);
1704 static int gs101_ufs_suspend(struct exynos_ufs *ufs)
1706 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1713 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1718 if (ufs->drv_data->suspend)
1719 ufs->drv_data->suspend(ufs);
1722 phy_power_off(ufs->phy);
1729 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1732 phy_power_on(ufs->phy);
1734 exynos_ufs_config_smu(ufs);
1776 struct exynos_ufs *ufs;
1779 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1780 if (!ufs)
1784 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1785 if (IS_ERR(ufs->reg_hci)) {
1787 return PTR_ERR(ufs->reg_hci);
1794 ufs->drv_data = device_get_match_data(dev);
1795 if (!ufs->drv_data)
1798 exynos_ufs_priv_init(hba, ufs);
1803 static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
1805 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1806 struct ufs_hba *hba = ufs->hba;
1810 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1814 for_each_ufs_tx_lane(ufs, i) {
1816 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1820 for_each_ufs_rx_lane(ufs, i) {
1822 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1838 exynos_ufs_establish_connt(ufs);
1843 static int fsd_ufs_post_link(struct exynos_ufs *ufs)
1846 struct ufs_hba *hba = ufs->hba;
1869 for_each_ufs_rx_lane(ufs, i) {
1881 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
1884 struct ufs_hba *hba = ufs->hba;
1892 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
1893 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
1894 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
1899 static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs)
1901 return (16 * 1000 * 1000000UL / ufs->mclk_rate);
1904 static int gs101_ufs_pre_link(struct exynos_ufs *ufs)
1906 struct ufs_hba *hba = ufs->hba;
1910 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate)
1912 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate)
1915 unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD);
1919 for_each_ufs_rx_lane(ufs, i) {
1921 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1934 for_each_ufs_tx_lane(ufs, i) {
1936 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1960 static int gs101_ufs_post_link(struct exynos_ufs *ufs)
1962 struct ufs_hba *hba = ufs->hba;
1968 hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN);
1977 static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs,
1980 struct ufs_hba *hba = ufs->hba;
1985 unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0);
1986 unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1);
1987 unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2);
1988 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
1989 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
1990 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
2187 { .compatible = "google,gs101-ufs",
2189 { .compatible = "samsung,exynos7-ufs",
2191 { .compatible = "samsung,exynosautov9-ufs",
2193 { .compatible = "samsung,exynosautov9-ufs-vh",
2195 { .compatible = "tesla,fsd-ufs",