1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/firmware/xlnx-zynqmp.h>
18 #include "ufshcd-dwc.h"
19 #include "ufshcd-pltfrm.h"
20 #include "ufshci-dwc.h"
26 #define MPHY_FW_CALIB_CFG_VAL		BIT(8)
58 	phy_write_attrs[1].mib_val = (u8)(addr >> 8);  in ufs_versal2_phy_reg_write()
60 	phy_write_attrs[3].mib_val = (u8)(val >> 8);  in ufs_versal2_phy_reg_write()
77 	phy_read_attrs[1].mib_val = (u8)(addr >> 8);  in ufs_versal2_phy_reg_read()
92 	*val |= (mib_val << 8);  in ufs_versal2_phy_reg_read()
125 			time_left--;  in ufs_versal2_enable_phy()
130 			dev_err(hba->dev, "Invalid Tx FSM state.\n");  in ufs_versal2_enable_phy()
131 			return -ETIMEDOUT;  in ufs_versal2_enable_phy()
145 			time_left--;  in ufs_versal2_enable_phy()
150 			dev_err(hba->dev, "Invalid Rx FSM state.\n");  in ufs_versal2_enable_phy()
151 			return -ETIMEDOUT;  in ufs_versal2_enable_phy()
164 	/* Bypass RX-AFE offset calibrations (ATT/CTLE) */  in ufs_versal2_setup_phy()
184 	if (host->attcompval0) {  in ufs_versal2_setup_phy()
185 		ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0);  in ufs_versal2_setup_phy()
190 	if (host->attcompval1) {  in ufs_versal2_setup_phy()
191 		ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1);  in ufs_versal2_setup_phy()
196 	if (host->ctlecompval0) {  in ufs_versal2_setup_phy()
197 		ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0);  in ufs_versal2_setup_phy()
202 	if (host->ctlecompval1) {  in ufs_versal2_setup_phy()
203 		ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1);  in ufs_versal2_setup_phy()
241 		time_left--;  in ufs_versal2_phy_init()
253 		dev_err(hba->dev, "Tx/Rx configuration signal busy.\n");  in ufs_versal2_phy_init()
254 		return -ETIMEDOUT;  in ufs_versal2_phy_init()
261 	ret = reset_control_deassert(host->rstphy);  in ufs_versal2_phy_init()
263 		dev_err(hba->dev, "ufsphy reset deassert failed, err = %d\n", ret);  in ufs_versal2_phy_init()
270 		time_left--;  in ufs_versal2_phy_init()
282 		dev_err(hba->dev, "SRAM initialization failed.\n");  in ufs_versal2_phy_init()
283 		return -ETIMEDOUT;  in ufs_versal2_phy_init()
296 	struct device *dev = hba->dev;  in ufs_versal2_init()
303 		return -ENOMEM;  in ufs_versal2_init()
305 	host->hba = hba;  in ufs_versal2_init()
308 	host->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;  in ufs_versal2_init()
310 	list_for_each_entry(clki, &hba->clk_list_head, list) {  in ufs_versal2_init()
311 		if (!strcmp(clki->name, "core"))  in ufs_versal2_init()
312 			host->host_clk = clk_get_rate(clki->clk);  in ufs_versal2_init()
315 	host->rstc = devm_reset_control_get_exclusive(dev, "host");  in ufs_versal2_init()
316 	if (IS_ERR(host->rstc)) {  in ufs_versal2_init()
318 		return PTR_ERR(host->rstc);  in ufs_versal2_init()
321 	host->rstphy = devm_reset_control_get_exclusive(dev, "phy");  in ufs_versal2_init()
322 	if (IS_ERR(host->rstphy)) {  in ufs_versal2_init()
324 		return PTR_ERR(host->rstphy);  in ufs_versal2_init()
327 	ret = reset_control_assert(host->rstc);  in ufs_versal2_init()
329 		dev_err(hba->dev, "host reset assert failed, err = %d\n", ret);  in ufs_versal2_init()
333 	ret = reset_control_assert(host->rstphy);  in ufs_versal2_init()
335 		dev_err(hba->dev, "phy reset assert failed, err = %d\n", ret);  in ufs_versal2_init()
345 	ret = reset_control_deassert(host->rstc);  in ufs_versal2_init()
347 		dev_err(hba->dev, "host reset deassert failed, err = %d\n", ret);  in ufs_versal2_init()
355 	host->attcompval0 = (u8)cal;  in ufs_versal2_init()
356 	host->attcompval1 = (u8)(cal >> 8);  in ufs_versal2_init()
357 	host->ctlecompval0 = (u8)(cal >> 16);  in ufs_versal2_init()
358 	host->ctlecompval1 = (u8)(cal >> 24);  in ufs_versal2_init()
360 	hba->quirks |= UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;  in ufs_versal2_init()
373 			dev_err(hba->dev, "Phy init failed (%d)\n", ret);  in ufs_versal2_hce_enable_notify()
387 		if (host->host_clk)  in ufs_versal2_link_startup_notify()
388 			ufshcd_writel(hba, host->host_clk / 1000000, DWC_UFS_REG_HCLKDIV);  in ufs_versal2_link_startup_notify()
395 		ret = -EINVAL;  in ufs_versal2_link_startup_notify()
432 			time_left--;  in ufs_versal2_phy_ratesel()
437 			dev_err(hba->dev, "Invalid Rx Ack value.\n");  in ufs_versal2_phy_ratesel()
438 			return -ETIMEDOUT;  in ufs_versal2_phy_ratesel()
457 		if (!host->attcompval0 && !host->attcompval1 && !host->ctlecompval0 &&  in ufs_versal2_pwr_change_notify()
458 		    !host->ctlecompval1) {  in ufs_versal2_pwr_change_notify()
459 			dev_req_params->pwr_rx = SLOW_MODE;  in ufs_versal2_pwr_change_notify()
460 			dev_req_params->pwr_tx = SLOW_MODE;  in ufs_versal2_pwr_change_notify()
464 		if (dev_req_params->pwr_rx == SLOW_MODE || dev_req_params->pwr_rx == SLOWAUTO_MODE)  in ufs_versal2_pwr_change_notify()
467 		if (dev_req_params->hs_rate == PA_HS_MODE_B)  in ufs_versal2_pwr_change_notify()
479 		ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 1);  in ufs_versal2_pwr_change_notify()
483 		ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 0);  in ufs_versal2_pwr_change_notify()
488 		for (lane = 0; lane < dev_req_params->lane_tx; lane++) {  in ufs_versal2_pwr_change_notify()
499 		if (dev_req_params->lane_tx == UFS_LANE_2 && dev_req_params->lane_rx == UFS_LANE_2)  in ufs_versal2_pwr_change_notify()
500 			ret = ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx,  in ufs_versal2_pwr_change_notify()
508 	.name			= "ufs-versal2-pltfm",
517 		.compatible = "amd,versal2-ufs",
526 	struct device *dev = &pdev->dev;  in ufs_versal2_probe()
541 	pm_runtime_get_sync(&(pdev)->dev);  in ufs_versal2_remove()
554 		.name	= "ufshcd-versal2",
563 MODULE_DESCRIPTION("AMD Versal Gen 2 UFS Host Controller driver");