23  * Return: 0 on success or non-zero value on failure.
28 		{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
29 		{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
30 		{ UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
31 		{ UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
32 		{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
33 		{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
34 		{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
35 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
37 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
39 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,  in tc_dwc_g210_setup_40bit_rmmi()
41 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_40bit_rmmi()
43 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
45 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
49 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
51 		{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
52 		{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
53 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
55 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_40bit_rmmi()
57 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_40bit_rmmi()
59 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_40bit_rmmi()
61 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_40bit_rmmi()
63 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
65 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
67 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_40bit_rmmi()
69 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_40bit_rmmi()
71 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
73 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
75 		{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
83  * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0.
86  * Return: 0 on success or non-zero value on failure.
91 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
93 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
95 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
97 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
99 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
101 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
105 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
107 		{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
108 		{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
109 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
111 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
113 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
115 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
117 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
119 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
121 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
123 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
125 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
127 		{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
138  * Return: 0 on success or non-zero value on failure.
142 	int connected_rx_lanes = 0;  in tc_dwc_g210_setup_20bit_rmmi_lane1()
143 	int connected_tx_lanes = 0;  in tc_dwc_g210_setup_20bit_rmmi_lane1()
144 	int ret = 0;  in tc_dwc_g210_setup_20bit_rmmi_lane1()
147 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
149 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
151 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
153 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
158 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
160 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
164 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
166 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
168 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
170 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
172 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
174 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
176 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
178 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
180 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
182 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
214  * Return: 0 on success or non-zero value on failure.
218 	int ret = 0;  in tc_dwc_g210_setup_20bit_rmmi()
221 		{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
222 		{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
223 		{ UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
224 		{ UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
225 		{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
226 		{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
227 		{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
235 	/* Lane 0 configuration*/  in tc_dwc_g210_setup_20bit_rmmi()
253  * Return: 0 on success non-zero value on failure.
257 	int ret = 0;  in tc_dwc_g210_config_40_bit()
267 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);  in tc_dwc_g210_config_40_bit()
272 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);  in tc_dwc_g210_config_40_bit()
283  * Return: 0 on success non-zero value on failure.
287 	int ret = 0;  in tc_dwc_g210_config_20_bit()
297 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);  in tc_dwc_g210_config_20_bit()
302 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);  in tc_dwc_g210_config_20_bit()