Lines Matching +full:wait +full:- +full:on +full:- +full:read

1 /* SPDX-License-Identifier: GPL-2.0 */
28 	unsigned int	tty_break;		/* Set on BREAK condition.  */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
81 #define RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
96 #define RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
97 #define RxINT_ALL	0x10	/* Int on all Rx Characters or error */
98 #define RxINT_ERR	0x18	/* Int on error only */
101 #define WT_RDY_RT	0x20	/* Wait/Ready on R/T */
102 #define WT_FN_RDYFN	0x40	/* Wait/FN/Ready FN */
103 #define WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 #define NORESET		0	/* No reset on write to R9 */
175 #define ABUNDER		4	/* Abort/flag on SDLC xmit underrun */
176 #define MARKIDLE	8	/* Mark/flag on idle */
177 #define GAOP		0x10	/* Go active on poll */
228 /* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
238 /* Read Register 1 (Special Receive Condition Status) */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
267 /* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
269 /* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
271 /* Read Register 8 (Receive Data) */
273 /* Read Register 10 (Miscellaneous Status Bits) */
274 #define ONLOOP		2	/* On loop */
279 /* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
281 /* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
283 /* Read Register 15 (External/Status Interrupt Control (WR15)) */