Lines Matching +full:1 +full:br +full:- +full:10
1 /* SPDX-License-Identifier: GPL-2.0 */
26 int clk_mode; /* May be 1, 16, 32, or 64. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
61 #define R1 1
70 #define R10 10
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
125 #define SB1 0x4 /* 1 stop bit/char */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
161 #define VIS 1 /* Vector Includes Status */
172 /* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
173 #define BIT6 1 /* 6 bit/8bit sync */
180 #define FM1 0x40 /* FM1 (transition = 1) */
186 #define TRxCTC 1 /* TRxC = Transmit clock */
187 #define TRxCBR 2 /* TRxC = BR Generator Output */
192 #define TCBR 0x10 /* Transmit clock = BR Generator output */
196 #define RCBR 0x40 /* Receive clock = BR Generator output */
205 #define BRENABL 1 /* Baud rate generator enable */
213 #define SSBR 0x80 /* Set DPLL source = BR generator */
219 #define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
238 /* Read Register 1 (Special Receive Condition Status) */
247 #define RES18 0xe /* 1/8 */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B). */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only). */
273 /* Read Register 10 (Miscellaneous Status Bits) */