Lines Matching +full:tegra264 +full:- +full:utc
1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 // NVIDIA Tegra UTC (UART Trace Controller) driver.
76 void __iomem *addr = tup->rx_base + offset; in tegra_utc_rx_readl()
83 void __iomem *addr = tup->rx_base + offset; in tegra_utc_rx_writel()
90 void __iomem *addr = tup->tx_base + offset; in tegra_utc_tx_readl()
97 void __iomem *addr = tup->tx_base + offset; in tegra_utc_tx_writel()
104 tup->tx_irqmask = TEGRA_UTC_INTR_REQ; in tegra_utc_enable_tx_irq()
106 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_MASK); in tegra_utc_enable_tx_irq()
107 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_SET); in tegra_utc_enable_tx_irq()
112 tup->tx_irqmask = 0x0; in tegra_utc_disable_tx_irq()
114 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_MASK); in tegra_utc_disable_tx_irq()
115 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_SET); in tegra_utc_disable_tx_irq()
131 tegra_utc_tx_writel(tup, tup->tx_threshold, TEGRA_UTC_FIFO_THRESHOLD); in tegra_utc_init_tx()
143 tup->rx_irqmask = TEGRA_UTC_INTR_REQ | TEGRA_UTC_INTR_TIMEOUT; in tegra_utc_init_rx()
146 tegra_utc_rx_writel(tup, tup->rx_threshold, TEGRA_UTC_FIFO_THRESHOLD); in tegra_utc_init_rx()
151 tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_MASK); in tegra_utc_init_rx()
152 tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_SET); in tegra_utc_init_rx()
160 struct uart_port *port = &tup->port; in tegra_utc_tx_chars()
173 struct tty_port *port = &tup->port.state->port; in tegra_utc_rx_chars()
179 while (max_chars--) { in tegra_utc_rx_chars()
185 tup->port.icount.rx++; in tegra_utc_rx_chars()
188 tup->port.icount.overrun++; in tegra_utc_rx_chars()
190 uart_port_unlock(&tup->port); in tegra_utc_rx_chars()
191 sysrq = uart_handle_sysrq_char(&tup->port, ch); in tegra_utc_rx_chars()
192 uart_port_lock(&tup->port); in tegra_utc_rx_chars()
207 uart_port_lock(&tup->port); in tegra_utc_isr()
211 status = tegra_utc_rx_readl(tup, TEGRA_UTC_INTR_STATUS) & tup->rx_irqmask; in tegra_utc_isr()
213 tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_CLEAR); in tegra_utc_isr()
221 status = tegra_utc_tx_readl(tup, TEGRA_UTC_INTR_STATUS) & tup->tx_irqmask; in tegra_utc_isr()
223 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_CLEAR); in tegra_utc_isr()
229 uart_port_unlock(&tup->port); in tegra_utc_isr()
262 tup->rx_irqmask = 0x0; in tegra_utc_stop_rx()
263 tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_MASK); in tegra_utc_stop_rx()
264 tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_SET); in tegra_utc_stop_rx()
280 /* Interrupt is dedicated to this UTC client. */ in tegra_utc_startup()
281 ret = request_irq(port->irq, tegra_utc_isr, 0, dev_name(port->dev), tup); in tegra_utc_startup()
283 dev_err(port->dev, "failed to register interrupt handler\n"); in tegra_utc_startup()
293 free_irq(port->irq, tup); in tegra_utc_shutdown()
299 /* The Tegra UTC clients supports only 8-N-1 configuration without HW flow control */ in tegra_utc_set_termios()
300 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); in tegra_utc_set_termios()
301 termios->c_cflag &= ~(CMSPAR | CRTSCTS); in tegra_utc_set_termios()
302 termios->c_cflag |= CS8 | CLOCAL; in tegra_utc_set_termios()
361 writel(c, port->membase + TEGRA_UTC_DATA); in tegra_utc_putc()
366 struct earlycon_device *dev = con->data; in tegra_utc_early_write()
371 burst_size -= readl(dev->port.membase + TEGRA_UTC_FIFO_OCCUPANCY); in tegra_utc_early_write()
375 uart_console_write(&dev->port, s, burst_size, tegra_utc_putc); in tegra_utc_early_write()
377 n -= burst_size; in tegra_utc_early_write()
384 if (!device->port.membase) in tegra_utc_early_console_setup()
385 return -ENODEV; in tegra_utc_early_console_setup()
389 device->port.membase + TEGRA_UTC_COMMAND); in tegra_utc_early_console_setup()
390 writel(TEGRA_UTC_DEFAULT_FIFO_THRESHOLD, device->port.membase + TEGRA_UTC_FIFO_THRESHOLD); in tegra_utc_early_console_setup()
393 writel(TEGRA_UTC_INTR_COMMON, device->port.membase + TEGRA_UTC_INTR_CLEAR); in tegra_utc_early_console_setup()
395 writel(0x0, device->port.membase + TEGRA_UTC_INTR_MASK); in tegra_utc_early_console_setup()
396 writel(0x0, device->port.membase + TEGRA_UTC_INTR_SET); in tegra_utc_early_console_setup()
399 writel(TEGRA_UTC_ENABLE_CLIENT_ENABLE, device->port.membase + TEGRA_UTC_ENABLE); in tegra_utc_early_console_setup()
401 device->con->write = tegra_utc_early_write; in tegra_utc_early_console_setup()
405 OF_EARLYCON_DECLARE(tegra_utc, "nvidia,tegra264-utc", tegra_utc_early_console_setup);
423 outbuf = wctxt->outbuf; in tegra_utc_console_write_atomic()
424 len = wctxt->len; in tegra_utc_console_write_atomic()
427 u32 burst_size = tup->fifosize; in tegra_utc_console_write_atomic()
429 burst_size -= tegra_utc_tx_readl(tup, TEGRA_UTC_FIFO_OCCUPANCY); in tegra_utc_console_write_atomic()
433 uart_console_write(&tup->port, outbuf, burst_size, tegra_utc_console_putchar); in tegra_utc_console_write_atomic()
436 len -= burst_size; in tegra_utc_console_write_atomic()
445 unsigned int len = READ_ONCE(wctxt->len); in tegra_utc_console_write_thread()
455 uart_console_write(&tup->port, wctxt->outbuf + i, 1, tegra_utc_console_putchar); in tegra_utc_console_write_thread()
465 struct uart_port *port = &tup->port; in tegra_utc_console_device_lock()
473 struct uart_port *port = &tup->port; in tegra_utc_console_device_unlock()
489 .driver_name = "tegra-utc",
496 tup->port.dev = dev; in tegra_utc_setup_port()
497 tup->port.fifosize = tup->fifosize; in tegra_utc_setup_port()
498 tup->port.flags = UPF_BOOT_AUTOCONF; in tegra_utc_setup_port()
499 tup->port.iotype = UPIO_MEM; in tegra_utc_setup_port()
500 tup->port.ops = &tegra_utc_uart_ops; in tegra_utc_setup_port()
501 tup->port.type = PORT_TEGRA_TCU; in tegra_utc_setup_port()
502 tup->port.private_data = tup; in tegra_utc_setup_port()
505 strscpy(tup->console.name, "ttyUTC", sizeof(tup->console.name)); in tegra_utc_setup_port()
506 tup->console.write_atomic = tegra_utc_console_write_atomic; in tegra_utc_setup_port()
507 tup->console.write_thread = tegra_utc_console_write_thread; in tegra_utc_setup_port()
508 tup->console.device_lock = tegra_utc_console_device_lock; in tegra_utc_setup_port()
509 tup->console.device_unlock = tegra_utc_console_device_unlock; in tegra_utc_setup_port()
510 tup->console.device = uart_console_device; in tegra_utc_setup_port()
511 tup->console.setup = tegra_utc_console_setup; in tegra_utc_setup_port()
512 tup->console.flags = CON_PRINTBUFFER | CON_NBCON; in tegra_utc_setup_port()
513 tup->console.data = &tegra_utc_driver; in tegra_utc_setup_port()
516 return uart_read_port_properties(&tup->port); in tegra_utc_setup_port()
523 ret = uart_add_one_port(&tegra_utc_driver, &tup->port); in tegra_utc_register_port()
528 register_console(&tup->console); in tegra_utc_register_port()
537 struct device *dev = &pdev->dev; in tegra_utc_probe()
543 return -ENOMEM; in tegra_utc_probe()
545 ret = device_property_read_u32(dev, "tx-threshold", &tup->tx_threshold); in tegra_utc_probe()
547 return dev_err_probe(dev, ret, "missing %s property\n", "tx-threshold"); in tegra_utc_probe()
549 ret = device_property_read_u32(dev, "rx-threshold", &tup->rx_threshold); in tegra_utc_probe()
551 return dev_err_probe(dev, ret, "missing %s property\n", "rx-threshold"); in tegra_utc_probe()
554 tup->fifosize = *soc_fifosize; in tegra_utc_probe()
556 tup->tx_base = devm_platform_ioremap_resource_byname(pdev, "tx"); in tegra_utc_probe()
557 if (IS_ERR(tup->tx_base)) in tegra_utc_probe()
558 return PTR_ERR(tup->tx_base); in tegra_utc_probe()
560 tup->rx_base = devm_platform_ioremap_resource_byname(pdev, "rx"); in tegra_utc_probe()
561 if (IS_ERR(tup->rx_base)) in tegra_utc_probe()
562 return PTR_ERR(tup->rx_base); in tegra_utc_probe()
578 unregister_console(&tup->console); in tegra_utc_remove()
580 uart_remove_one_port(&tegra_utc_driver, &tup->port); in tegra_utc_remove()
586 { .compatible = "nvidia,tegra264-utc", .data = &tegra264_utc_soc },
595 .name = "tegra-utc",