Lines Matching +full:1 +full:br +full:- +full:10
1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
32 #define R1 1
41 #define R10 10
61 /* Write Register 1 */
99 #define SB1 0x4 /* 1 stop bit/char */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
133 #define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
144 #define VIS 1 /* Vector Includes Status */
155 /* Write Register 10 (misc control bits) */
156 #define BIT6 1 /* 6 bit/8bit sync */
163 #define FM1 0x40 /* FM1 (transition = 1) */
169 #define TRxCTC 1 /* TRxC = Transmit clock */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
179 #define RCBR 0x40 /* Receive clock = BR Generator output */
188 #define BRENAB 1 /* Baud rate generator enable */
196 #define SSBR 0x80 /* Set DPLL source = BR generator */
202 #define WR7pEN 1 /* WR7' Enable (ESCC only) */
222 /* Read Register 1 */
231 #define RES18 0xe /* 1/8 */
239 /* Read Register 2 (channel b only) - Interrupt vector */
264 /* Read Register 10 (misc status bits) */
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
285 sbus_readb(&channel->data); \
287 sbus_readb(&channel->data); \