Lines Matching +full:sci +full:- +full:reset
1 /* SPDX-License-Identifier: GPL-2.0 */
11 * SCI register subset common for all port types.
40 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
41 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
42 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
60 /* Serial Control Register, SCI only bits */
67 /* Serial Control Register, HSCIF-only bits */
70 /* SCxSR (Serial Status Register) on SCI */
114 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
115 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
162 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
163 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
164 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
165 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
166 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
167 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
169 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
172 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
174 (to_sci_port(port)->params->error_clear)
176 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
178 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)