Lines Matching +full:clock +full:- +full:error +full:- +full:detect
1 /* SPDX-License-Identifier: GPL-2.0 */
31 SCCKS, /* BRG Clock Select Register */
40 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
41 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
42 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
46 #define SCSMR_CKS 0x0003 /* Clock Select */
49 #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
67 /* Serial Control Register, HSCIF-only bits */
73 #define SCI_ORER BIT(5) /* Overrun Error */
74 #define SCI_FER BIT(4) /* Framing Error */
75 #define SCI_PER BIT(3) /* Parity Error */
87 #define SCIF_ER BIT(7) /* Receive Error */
90 #define SCIF_BRK BIT(4) /* Break Detect */
91 #define SCIF_FER BIT(3) /* Framing Error */
92 #define SCIF_PER BIT(2) /* Parity Error */
99 #define SCIFA_ORER BIT(9) /* Overrun Error */
120 #define SCLSR_ORER BIT(0) /* Overrun Error */
127 #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
128 #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
154 * BRG Clock Select Register (Some SCIF and HSCIF)
155 * The Baud Rate Generator for external clock can provide a clock source for
156 * the sampling clock. It outputs either its frequency divided clock, or the
157 * (undivided) (H)SCK external clock.
160 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
162 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
163 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
164 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
165 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
166 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
167 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
169 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
172 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
174 (to_sci_port(port)->params->error_clear)
176 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
178 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)