Lines Matching +full:0 +full:x0f00
41 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
46 #define SCSMR_CKS 0x0003 /* Clock Select */
50 #define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
51 #define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
52 #define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
53 #define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
54 #define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
55 #define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
56 #define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
57 #define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
58 #define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
77 #define SCI_RESERVED 0x03 /* All reserved bits */
94 #define SCIF_DR BIT(0) /* Receive Data Ready */
96 #define SCIF_PERC 0xf000 /* Number of Parity Errors */
97 #define SCIF_FERC 0x0f00 /* Number of Framing Errors */
116 #define SCFCR_LOOP BIT(0) /* Loopback Test */
120 #define SCLSR_ORER BIT(0) /* Overrun Error */
130 #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
137 #define HSCIF_SRHP_MASK 0x0f00
144 #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */
151 #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */
159 #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
160 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
167 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)