255 static struct sci_port sci_ports[SCI_NPORTS];  variable
3409 	struct sci_port *sci_port = &sci_ports[co->index];  in serial_console_write()
3464 	sci_port = &sci_ports[co->index];  in serial_console_setup()
3520 	struct sci_port *sp = &sci_ports[pdev->id];  in sci_probe_earlyprintk()
3772 	if (id >= ARRAY_SIZE(sci_ports)) {  in sci_parse_dt()
3777 	sp = &sci_ports[id];  in sci_parse_dt()
3844 	if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {  in sci_probe_single()
3893 		sp = &sci_ports[dev_id];  in sci_probe()
3902 		sp = &sci_ports[dev_id];  in sci_probe()
3930 	if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)  in sci_probe()
4034 	struct sci_port *sci_port = &sci_ports[0];  in early_console_exit()
4058 	sci_ports[0].port = device->port;  in scix_early_console_setup()
4059 	sci_ports[0].type = data->type;  in scix_early_console_setup()
4060 	sci_ports[0].regtype = data->regtype;  in scix_early_console_setup()
4065 	sci_ports[0].cfg = &port_cfg;  in scix_early_console_setup()
4066 	sci_ports[0].params = data->params;  in scix_early_console_setup()
4067 	sci_ports[0].ops = data->ops;  in scix_early_console_setup()
4068 	sci_ports[0].port.ops = data->uart_ops;  in scix_early_console_setup()
4070 	regs = sci_ports[0].params->common_regs;  in scix_early_console_setup()
4072 	port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);  in scix_early_console_setup()
4073 	sci_ports[0].ops->write_reg(&sci_ports[0].port,  in scix_early_console_setup()
4075 				    sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);  in scix_early_console_setup()