Lines Matching +full:mixed +full:- +full:signals
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
26 #include <linux/dma-mapping.h>
58 #include "sh-sci.h"
60 /* Offsets into the sci_port->irqs array */
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
269 * Common SH-2(A) SCIF definitions for ports with FIFO data
324 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
325 * TEI-DRI, RXI-EDGE and TXI-EDGE.
326 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
327 * - SCFCR register does not have SCFCR_MCE bit.
328 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
353 * Common SH-3 SCIF definitions.
375 * Common SH-4(A) SCIF(B) definitions.
455 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
479 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
506 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
529 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
541 if (reg->size == 8) in sci_serial_in()
542 return ioread8(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
543 else if (reg->size == 16) in sci_serial_in()
544 return ioread16(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
555 if (reg->size == 8) in sci_serial_out()
556 iowrite8(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
557 else if (reg->size == 16) in sci_serial_out()
558 iowrite16(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
567 if (!sci_port->port.dev) in sci_port_enable()
570 pm_runtime_get_sync(sci_port->port.dev); in sci_port_enable()
573 clk_prepare_enable(sci_port->clks[i]); in sci_port_enable()
574 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); in sci_port_enable()
576 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; in sci_port_enable()
583 if (!sci_port->port.dev) in sci_port_disable()
586 for (i = SCI_NUM_CLKS; i-- > 0; ) in sci_port_disable()
587 clk_disable_unprepare(sci_port->clks[i]); in sci_port_disable()
589 pm_runtime_put_sync(sci_port->port.dev); in sci_port_disable()
596 * special-casing the port type, we check the port initialization in port_rx_irq_mask()
601 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); in port_rx_irq_mask()
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
612 if (s->chan_tx) in sci_start_tx()
620 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && in sci_start_tx()
621 dma_submit_error(s->cookie_tx)) { in sci_start_tx()
622 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_start_tx()
624 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); in sci_start_tx()
626 s->cookie_tx = 0; in sci_start_tx()
627 schedule_work(&s->work_tx); in sci_start_tx()
631 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || in sci_start_tx()
632 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
641 if (port->type == PORT_SCI) in sci_start_tx()
655 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_tx()
663 if (to_sci_port(port)->chan_tx && in sci_stop_tx()
664 !dma_submit_error(to_sci_port(port)->cookie_tx)) { in sci_stop_tx()
665 dmaengine_terminate_async(to_sci_port(port)->chan_tx); in sci_stop_tx()
666 to_sci_port(port)->cookie_tx = -EINVAL; in sci_stop_tx()
677 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_start_rx()
689 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_rx()
699 if (port->type == PORT_SCI) { in sci_clear_SCxSR()
702 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { in sci_clear_SCxSR()
762 * Use port-specific handler if provided. in sci_init_pins()
764 if (s->cfg->ops && s->cfg->ops->init_pins) { in sci_init_pins()
765 s->cfg->ops->init_pins(port, cflag); in sci_init_pins()
769 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_init_pins()
775 if (to_sci_port(port)->has_rtscts) { in sci_init_pins()
777 if (!(port->mctrl & TIOCM_RTS)) { in sci_init_pins()
780 } else if (!s->autorts) { in sci_init_pins()
792 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { in sci_init_pins()
797 if (!(port->mctrl & TIOCM_RTS)) in sci_init_pins()
799 else if (!s->autorts) in sci_init_pins()
810 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_txfill()
814 if (reg->size) in sci_txfill()
818 if (reg->size) in sci_txfill()
826 return port->fifosize - sci_txfill(port); in sci_txroom()
832 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_rxfill()
836 if (reg->size) in sci_rxfill()
840 if (reg->size) in sci_rxfill()
852 struct tty_port *tport = &port->state->port; in sci_transmit_chars()
862 if (kfifo_is_empty(&tport->xmit_fifo)) in sci_transmit_chars()
875 if (port->x_char) { in sci_transmit_chars()
876 c = port->x_char; in sci_transmit_chars()
877 port->x_char = 0; in sci_transmit_chars()
878 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { in sci_transmit_chars()
879 if (port->type == PORT_SCI && in sci_transmit_chars()
880 kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
890 s->tx_occurred = true; in sci_transmit_chars()
892 port->icount.tx++; in sci_transmit_chars()
893 } while (--count > 0); in sci_transmit_chars()
897 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_transmit_chars()
899 if (kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
900 if (port->type == PORT_SCI) { in sci_transmit_chars()
913 struct tty_port *tport = &port->state->port; in sci_receive_chars()
930 if (port->type == PORT_SCI) { in sci_receive_chars()
940 if (port->type == PORT_SCIF || in sci_receive_chars()
941 port->type == PORT_HSCIF) { in sci_receive_chars()
949 count--; i--; in sci_receive_chars()
956 port->icount.frame++; in sci_receive_chars()
959 port->icount.parity++; in sci_receive_chars()
971 port->icount.rx += count; in sci_receive_chars()
989 struct tty_port *tport = &port->state->port; in sci_handle_errors()
993 if (status & s->params->overrun_mask) { in sci_handle_errors()
994 port->icount.overrun++; in sci_handle_errors()
1003 port->icount.frame++; in sci_handle_errors()
1011 port->icount.parity++; in sci_handle_errors()
1025 struct tty_port *tport = &port->state->port; in sci_handle_fifo_overrun()
1031 reg = sci_getreg(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1032 if (!reg->size) in sci_handle_fifo_overrun()
1035 status = sci_serial_in(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1036 if (status & s->params->overrun_mask) { in sci_handle_fifo_overrun()
1037 status &= ~s->params->overrun_mask; in sci_handle_fifo_overrun()
1038 sci_serial_out(port, s->params->overrun_reg, status); in sci_handle_fifo_overrun()
1040 port->icount.overrun++; in sci_handle_fifo_overrun()
1054 struct tty_port *tport = &port->state->port; in sci_handle_breaks()
1060 port->icount.brk++; in sci_handle_breaks()
1079 if (rx_trig >= port->fifosize) in scif_set_rtrg()
1080 rx_trig = port->fifosize - 1; in scif_set_rtrg()
1085 if (sci_getreg(port, HSRTRGR)->size) { in scif_set_rtrg()
1090 switch (port->type) { in scif_set_rtrg()
1136 if (sci_getreg(port, HSRTRGR)->size) in scif_rtrg_enabled()
1146 struct uart_port *port = &s->port; in rx_fifo_timer_fn()
1148 dev_dbg(port->dev, "Rx timed out\n"); in rx_fifo_timer_fn()
1158 return sprintf(buf, "%d\n", sci->rx_trigger); in rx_fifo_trigger_show()
1174 sci->rx_trigger = scif_set_rtrg(port, r); in rx_fifo_trigger_store()
1175 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in rx_fifo_trigger_store()
1191 if (port->type == PORT_HSCIF) in rx_fifo_timeout_show()
1192 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; in rx_fifo_timeout_show()
1194 v = sci->rx_fifo_timeout; in rx_fifo_timeout_show()
1213 if (port->type == PORT_HSCIF) { in rx_fifo_timeout_store()
1215 return -EINVAL; in rx_fifo_timeout_store()
1216 sci->hscif_tot = r << HSSCR_TOT_SHIFT; in rx_fifo_timeout_store()
1218 sci->rx_fifo_timeout = r; in rx_fifo_timeout_store()
1221 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); in rx_fifo_timeout_store()
1234 struct uart_port *port = &s->port; in sci_dma_tx_complete()
1235 struct tty_port *tport = &port->state->port; in sci_dma_tx_complete()
1238 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_dma_tx_complete()
1242 uart_xmit_advance(port, s->tx_dma_len); in sci_dma_tx_complete()
1244 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_dma_tx_complete()
1247 s->tx_occurred = true; in sci_dma_tx_complete()
1249 if (!kfifo_is_empty(&tport->xmit_fifo)) { in sci_dma_tx_complete()
1250 s->cookie_tx = 0; in sci_dma_tx_complete()
1251 schedule_work(&s->work_tx); in sci_dma_tx_complete()
1253 s->cookie_tx = -EINVAL; in sci_dma_tx_complete()
1254 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_tx_complete()
1255 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1258 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1260 dmaengine_pause(s->chan_tx_saved); in sci_dma_tx_complete()
1261 enable_irq(s->irqs[SCIx_TXI_IRQ]); in sci_dma_tx_complete()
1272 struct uart_port *port = &s->port; in sci_dma_rx_push()
1273 struct tty_port *tport = &port->state->port; in sci_dma_rx_push()
1278 port->icount.buf_overrun++; in sci_dma_rx_push()
1280 port->icount.rx += copied; in sci_dma_rx_push()
1289 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_find_active()
1290 if (s->active_rx == s->cookie_rx[i]) in sci_dma_rx_find_active()
1293 return -1; in sci_dma_rx_find_active()
1301 s->chan_rx = NULL; in sci_dma_rx_chan_invalidate()
1302 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_chan_invalidate()
1303 s->cookie_rx[i] = -EINVAL; in sci_dma_rx_chan_invalidate()
1304 s->active_rx = 0; in sci_dma_rx_chan_invalidate()
1309 struct dma_chan *chan = s->chan_rx_saved; in sci_dma_rx_release()
1310 struct uart_port *port = &s->port; in sci_dma_rx_release()
1314 s->chan_rx_saved = NULL; in sci_dma_rx_release()
1319 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], in sci_dma_rx_release()
1320 sg_dma_address(&s->sg_rx[0])); in sci_dma_rx_release()
1335 struct uart_port *port = &s->port; in sci_dma_rx_reenable_irq()
1340 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_reenable_irq()
1341 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_rx_reenable_irq()
1342 enable_irq(s->irqs[SCIx_RXI_IRQ]); in sci_dma_rx_reenable_irq()
1343 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_reenable_irq()
1344 scif_set_rtrg(port, s->rx_trigger); in sci_dma_rx_reenable_irq()
1354 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_complete()
1355 struct uart_port *port = &s->port; in sci_dma_rx_complete()
1360 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, in sci_dma_rx_complete()
1361 s->active_rx); in sci_dma_rx_complete()
1363 hrtimer_cancel(&s->rx_timer); in sci_dma_rx_complete()
1369 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); in sci_dma_rx_complete()
1372 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_complete()
1374 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, in sci_dma_rx_complete()
1380 desc->callback = sci_dma_rx_complete; in sci_dma_rx_complete()
1381 desc->callback_param = s; in sci_dma_rx_complete()
1382 s->cookie_rx[active] = dmaengine_submit(desc); in sci_dma_rx_complete()
1383 if (dma_submit_error(s->cookie_rx[active])) in sci_dma_rx_complete()
1386 s->active_rx = s->cookie_rx[!active]; in sci_dma_rx_complete()
1391 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", in sci_dma_rx_complete()
1392 __func__, s->cookie_rx[active], active, s->active_rx); in sci_dma_rx_complete()
1394 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_dma_rx_complete()
1404 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); in sci_dma_rx_complete()
1409 struct dma_chan *chan = s->chan_tx_saved; in sci_dma_tx_release()
1411 cancel_work_sync(&s->work_tx); in sci_dma_tx_release()
1412 s->chan_tx_saved = s->chan_tx = NULL; in sci_dma_tx_release()
1413 s->cookie_tx = -EINVAL; in sci_dma_tx_release()
1415 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, in sci_dma_tx_release()
1422 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_submit()
1423 struct uart_port *port = &s->port; in sci_dma_rx_submit()
1428 struct scatterlist *sg = &s->sg_rx[i]; in sci_dma_rx_submit()
1437 desc->callback = sci_dma_rx_complete; in sci_dma_rx_submit()
1438 desc->callback_param = s; in sci_dma_rx_submit()
1439 s->cookie_rx[i] = dmaengine_submit(desc); in sci_dma_rx_submit()
1440 if (dma_submit_error(s->cookie_rx[i])) in sci_dma_rx_submit()
1445 s->active_rx = s->cookie_rx[0]; in sci_dma_rx_submit()
1460 return -EAGAIN; in sci_dma_rx_submit()
1467 struct dma_chan *chan = s->chan_tx; in sci_dma_tx_work_fn()
1468 struct uart_port *port = &s->port; in sci_dma_tx_work_fn()
1469 struct tty_port *tport = &port->state->port; in sci_dma_tx_work_fn()
1482 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, in sci_dma_tx_work_fn()
1484 buf = s->tx_dma_addr + tail; in sci_dma_tx_work_fn()
1485 if (!s->tx_dma_len) { in sci_dma_tx_work_fn()
1491 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1496 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1500 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1503 desc->callback = sci_dma_tx_complete; in sci_dma_tx_work_fn()
1504 desc->callback_param = s; in sci_dma_tx_work_fn()
1505 s->cookie_tx = dmaengine_submit(desc); in sci_dma_tx_work_fn()
1506 if (dma_submit_error(s->cookie_tx)) { in sci_dma_tx_work_fn()
1508 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1513 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", in sci_dma_tx_work_fn()
1514 __func__, tport->xmit_buf, tail, s->cookie_tx); in sci_dma_tx_work_fn()
1521 s->chan_tx = NULL; in sci_dma_tx_work_fn()
1530 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_timer_fn()
1531 struct uart_port *port = &s->port; in sci_dma_rx_timer_fn()
1538 dev_dbg(port->dev, "DMA Rx timed out\n"); in sci_dma_rx_timer_fn()
1548 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1551 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", in sci_dma_rx_timer_fn()
1552 s->active_rx, active); in sci_dma_rx_timer_fn()
1566 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1569 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); in sci_dma_rx_timer_fn()
1574 dmaengine_terminate_async(s->chan_rx); in sci_dma_rx_timer_fn()
1575 read = sg_dma_len(&s->sg_rx[active]) - state.residue; in sci_dma_rx_timer_fn()
1578 count = sci_dma_rx_push(s, s->rx_buf[active], read); in sci_dma_rx_timer_fn()
1580 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_timer_fn()
1583 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_timer_fn()
1584 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_timer_fn()
1601 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); in sci_request_dma_chan()
1603 dev_dbg(port->dev, "dma_request_chan failed\n"); in sci_request_dma_chan()
1609 cfg.dst_addr = port->mapbase + in sci_request_dma_chan()
1610 (sci_getreg(port, SCxTDR)->offset << port->regshift); in sci_request_dma_chan()
1612 cfg.src_addr = port->mapbase + in sci_request_dma_chan()
1613 (sci_getreg(port, SCxRDR)->offset << port->regshift); in sci_request_dma_chan()
1618 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); in sci_request_dma_chan()
1629 struct tty_port *tport = &port->state->port; in sci_request_dma()
1632 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); in sci_request_dma()
1641 if (!port->dev->of_node) in sci_request_dma()
1644 s->cookie_tx = -EINVAL; in sci_request_dma()
1650 if (!of_property_present(port->dev->of_node, "dmas")) in sci_request_dma()
1654 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); in sci_request_dma()
1657 s->tx_dma_addr = dma_map_single(chan->device->dev, in sci_request_dma()
1658 tport->xmit_buf, in sci_request_dma()
1661 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { in sci_request_dma()
1662 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); in sci_request_dma()
1665 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", in sci_request_dma()
1667 tport->xmit_buf, &s->tx_dma_addr); in sci_request_dma()
1669 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); in sci_request_dma()
1670 s->chan_tx_saved = s->chan_tx = chan; in sci_request_dma()
1675 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); in sci_request_dma()
1681 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); in sci_request_dma()
1682 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, in sci_request_dma()
1685 dev_warn(port->dev, in sci_request_dma()
1692 struct scatterlist *sg = &s->sg_rx[i]; in sci_request_dma()
1695 s->rx_buf[i] = buf; in sci_request_dma()
1697 sg_dma_len(sg) = s->buf_len_rx; in sci_request_dma()
1699 buf += s->buf_len_rx; in sci_request_dma()
1700 dma += s->buf_len_rx; in sci_request_dma()
1703 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in sci_request_dma()
1704 s->rx_timer.function = sci_dma_rx_timer_fn; in sci_request_dma()
1706 s->chan_rx_saved = s->chan_rx = chan; in sci_request_dma()
1708 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_request_dma()
1709 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_request_dma()
1718 if (s->chan_tx_saved) in sci_free_dma()
1720 if (s->chan_rx_saved) in sci_free_dma()
1733 s->tx_dma_len = 0; in sci_flush_buffer()
1734 if (s->chan_tx) { in sci_flush_buffer()
1735 dmaengine_terminate_async(s->chan_tx); in sci_flush_buffer()
1736 s->cookie_tx = -EINVAL; in sci_flush_buffer()
1745 if (!s->chan_tx) in sci_dma_check_tx_occurred()
1748 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); in sci_dma_check_tx_occurred()
1750 s->tx_occurred = true; in sci_dma_check_tx_occurred()
1774 if (s->chan_rx) { in sci_rx_interrupt()
1779 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_rx_interrupt()
1780 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1781 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); in sci_rx_interrupt()
1782 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1798 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", in sci_rx_interrupt()
1799 jiffies, s->rx_timeout); in sci_rx_interrupt()
1800 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_rx_interrupt()
1808 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { in sci_rx_interrupt()
1810 scif_set_rtrg(port, s->rx_trigger); in sci_rx_interrupt()
1812 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( in sci_rx_interrupt()
1813 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); in sci_rx_interrupt()
1843 if (port->type != PORT_SCI) in sci_tx_end_interrupt()
1875 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { in sci_er_interrupt()
1889 if (port->type == PORT_SCI) { in sci_er_interrupt()
1897 if (!s->chan_rx) in sci_er_interrupt()
1904 if (!s->chan_tx) in sci_er_interrupt()
1919 if (s->params->overrun_reg == SCxSR) in sci_mpxed_interrupt()
1921 else if (sci_getreg(port, s->params->overrun_reg)->size) in sci_mpxed_interrupt()
1922 orer_status = sci_serial_in(port, s->params->overrun_reg); in sci_mpxed_interrupt()
1928 !s->chan_tx) in sci_mpxed_interrupt()
1935 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && in sci_mpxed_interrupt()
1944 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && in sci_mpxed_interrupt()
1949 if (orer_status & s->params->overrun_mask) { in sci_mpxed_interrupt()
2005 struct uart_port *up = &port->port; in sci_request_irq()
2014 if (port->irqs[w] == port->irqs[i]) in sci_request_irq()
2021 irq = up->irq; in sci_request_irq()
2023 irq = port->irqs[i]; in sci_request_irq()
2034 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", in sci_request_irq()
2035 dev_name(up->dev), desc->desc); in sci_request_irq()
2036 if (!port->irqstr[j]) { in sci_request_irq()
2037 ret = -ENOMEM; in sci_request_irq()
2041 ret = request_irq(irq, desc->handler, up->irqflags, in sci_request_irq()
2042 port->irqstr[j], port); in sci_request_irq()
2044 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); in sci_request_irq()
2052 while (--i >= 0) in sci_request_irq()
2053 free_irq(port->irqs[i], port); in sci_request_irq()
2056 while (--j >= 0) in sci_request_irq()
2057 kfree(port->irqstr[j]); in sci_request_irq()
2071 int irq = port->irqs[i]; in sci_free_irq()
2082 if (port->irqs[j] == irq) in sci_free_irq()
2087 free_irq(port->irqs[i], port); in sci_free_irq()
2088 kfree(port->irqstr[i]); in sci_free_irq()
2105 if (!s->tx_occurred) in sci_tx_empty()
2113 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_rts()
2126 } else if (sci_getreg(port, SCSPTR)->size) { in sci_set_rts()
2140 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_get_cts()
2143 } else if (sci_getreg(port, SCSPTR)->size) { in sci_get_cts()
2152 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2155 * handled via the ->init_pins() op, which is a bit of a one-way street,
2156 * lacking any ability to defer pin control -- this will later be
2174 if (reg->size) in sci_set_mctrl()
2179 mctrl_gpio_set(s->gpios, mctrl); in sci_set_mctrl()
2181 if (!s->has_rtscts) in sci_set_mctrl()
2186 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2192 } else if (s->autorts) { in sci_set_mctrl()
2193 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_mctrl()
2200 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2212 struct mctrl_gpios *gpios = s->gpios; in sci_get_mctrl()
2221 if (s->autorts) { in sci_get_mctrl()
2237 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); in sci_enable_ms()
2246 if (!sci_getreg(port, SCSPTR)->size) { in sci_break_ctl()
2258 if (break_state == -1) { in sci_break_ctl()
2276 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_startup()
2278 s->tx_occurred = false; in sci_startup()
2296 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_shutdown()
2298 s->autorts = false; in sci_shutdown()
2299 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); in sci_shutdown()
2310 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); in sci_shutdown()
2314 if (s->chan_rx_saved) { in sci_shutdown()
2315 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, in sci_shutdown()
2316 port->line); in sci_shutdown()
2317 hrtimer_cancel(&s->rx_timer); in sci_shutdown()
2321 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) in sci_shutdown()
2322 del_timer_sync(&s->rx_fifo_timer); in sci_shutdown()
2330 unsigned long freq = s->clk_rates[SCI_SCK]; in sci_sck_calc()
2334 if (s->port.type != PORT_HSCIF) in sci_sck_calc()
2338 err = DIV_ROUND_CLOSEST(freq, sr) - bps; in sci_sck_calc()
2343 *srr = sr - 1; in sci_sck_calc()
2349 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, in sci_sck_calc()
2361 if (s->port.type != PORT_HSCIF) in sci_brg_calc()
2368 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; in sci_brg_calc()
2374 *srr = sr - 1; in sci_brg_calc()
2380 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, in sci_brg_calc()
2390 unsigned long freq = s->clk_rates[SCI_FCK]; in sci_scbrr_calc()
2394 if (s->port.type != PORT_HSCIF) in sci_scbrr_calc()
2408 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - in sci_scbrr_calc()
2409 * (|D - 0.5| / N * (1 + F))| in sci_scbrr_calc()
2421 * err = freq / (br * prediv) - bps in sci_scbrr_calc()
2433 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
2438 *brr = br - 1; in sci_scbrr_calc()
2439 *srr = sr - 1; in sci_scbrr_calc()
2448 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, in sci_scbrr_calc()
2459 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ in sci_reset()
2462 if (reg->size) in sci_reset()
2468 if (sci_getreg(port, SCLSR)->size) { in sci_reset()
2474 if (s->rx_trigger > 1) { in sci_reset()
2475 if (s->rx_fifo_timeout) { in sci_reset()
2477 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); in sci_reset()
2479 if (port->type == PORT_SCIFA || in sci_reset()
2480 port->type == PORT_SCIFB) in sci_reset()
2483 scif_set_rtrg(port, s->rx_trigger); in sci_reset()
2498 int best_clk = -1; in sci_set_termios()
2501 if ((termios->c_cflag & CSIZE) == CS7) { in sci_set_termios()
2504 termios->c_cflag &= ~CSIZE; in sci_set_termios()
2505 termios->c_cflag |= CS8; in sci_set_termios()
2507 if (termios->c_cflag & PARENB) in sci_set_termios()
2509 if (termios->c_cflag & PARODD) in sci_set_termios()
2511 if (termios->c_cflag & CSTOPB) in sci_set_termios()
2515 * earlyprintk comes here early on with port->uartclk set to zero. in sci_set_termios()
2518 * the baud rate is not programmed during earlyprintk - it is assumed in sci_set_termios()
2522 if (!port->uartclk) { in sci_set_termios()
2528 max_freq = max(max_freq, s->clk_rates[i]); in sci_set_termios()
2540 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && in sci_set_termios()
2541 port->type != PORT_SCIFB) { in sci_set_termios()
2555 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2556 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, in sci_set_termios()
2571 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2572 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, in sci_set_termios()
2599 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", in sci_set_termios()
2600 s->clks[best_clk], baud, min_err); in sci_set_termios()
2608 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { in sci_set_termios()
2617 uart_update_timeout(port, termios->c_cflag, baud); in sci_set_termios()
2620 bits = tty_get_frame_size(termios->c_cflag); in sci_set_termios()
2622 if (sci_getreg(port, SEMR)->size) in sci_set_termios()
2626 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_set_termios()
2638 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2641 if (sci_getreg(port, HSSRR)->size) { in sci_set_termios()
2646 int last_stop = bits * 2 - 1; in sci_set_termios()
2656 int shift = clamp(deviation / 2, -8, 7); in sci_set_termios()
2666 udelay((1000000 + (baud - 1)) / baud); in sci_set_termios()
2669 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); in sci_set_termios()
2672 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2676 sci_init_pins(port, termios->c_cflag); in sci_set_termios()
2678 port->status &= ~UPSTAT_AUTOCTS; in sci_set_termios()
2679 s->autorts = false; in sci_set_termios()
2681 if (reg->size) { in sci_set_termios()
2684 if ((port->flags & UPF_HARD_FLOW) && in sci_set_termios()
2685 (termios->c_cflag & CRTSCTS)) { in sci_set_termios()
2687 port->status |= UPSTAT_AUTOCTS; in sci_set_termios()
2689 s->autorts = true; in sci_set_termios()
2701 if (port->flags & UPF_HARD_FLOW) { in sci_set_termios()
2703 sci_set_mctrl(port, port->mctrl); in sci_set_termios()
2711 if (port->type != PORT_SCI) in sci_set_termios()
2713 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); in sci_set_termios()
2714 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2716 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { in sci_set_termios()
2727 s->rx_frame = (10000 * bits) / (baud / 100); in sci_set_termios()
2729 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; in sci_set_termios()
2732 if ((termios->c_cflag & CREAD) != 0) in sci_set_termios()
2739 if (UART_ENABLE_MS(port, termios->c_cflag)) in sci_set_termios()
2760 switch (port->type) { in sci_type()
2785 if (port->membase) in sci_remap_port()
2788 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_remap_port()
2789 port->membase = ioremap(port->mapbase, sport->reg_size); in sci_remap_port()
2790 if (unlikely(!port->membase)) { in sci_remap_port()
2791 dev_err(port->dev, "can't remap port#%d\n", port->line); in sci_remap_port()
2792 return -ENXIO; in sci_remap_port()
2800 port->membase = (void __iomem *)(uintptr_t)port->mapbase; in sci_remap_port()
2810 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_release_port()
2811 iounmap(port->membase); in sci_release_port()
2812 port->membase = NULL; in sci_release_port()
2815 release_mem_region(port->mapbase, sport->reg_size); in sci_release_port()
2824 res = request_mem_region(port->mapbase, sport->reg_size, in sci_request_port()
2825 dev_name(port->dev)); in sci_request_port()
2827 dev_err(port->dev, "request_mem_region failed."); in sci_request_port()
2828 return -EBUSY; in sci_request_port()
2845 port->type = sport->cfg->type; in sci_config_port()
2852 if (ser->baud_base < 2400) in sci_verify_port()
2854 return -EINVAL; in sci_verify_port()
2895 if (sci_port->cfg->type == PORT_HSCIF) in sci_init_clocks()
2921 sci_port->clks[i] = clk; in sci_init_clocks()
2931 if (cfg->regtype != SCIx_PROBE_REGTYPE) in sci_probe_regmap()
2932 return &sci_port_params[cfg->regtype]; in sci_probe_regmap()
2934 switch (cfg->type) { in sci_probe_regmap()
2949 * The SH-4 is a bit of a misnomer here, although that's in sci_probe_regmap()
2971 struct uart_port *port = &sci_port->port; in sci_init_single()
2976 sci_port->cfg = p; in sci_init_single()
2978 port->ops = &sci_uart_ops; in sci_init_single()
2979 port->iotype = UPIO_MEM; in sci_init_single()
2980 port->line = index; in sci_init_single()
2981 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); in sci_init_single()
2985 return -ENOMEM; in sci_init_single()
2987 port->mapbase = res->start; in sci_init_single()
2988 sci_port->reg_size = resource_size(res); in sci_init_single()
2990 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { in sci_init_single()
2992 sci_port->irqs[i] = platform_get_irq_optional(dev, i); in sci_init_single()
2994 sci_port->irqs[i] = platform_get_irq(dev, i); in sci_init_single()
3001 if (p->type == PORT_SCI) in sci_init_single()
3002 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); in sci_init_single()
3007 * In the non-muxed case, up to 6 interrupt signals might be generated in sci_init_single()
3008 * from the SCI, however those signals might have their own individual in sci_init_single()
3011 if (sci_port->irqs[0] < 0) in sci_init_single()
3012 return -ENXIO; in sci_init_single()
3014 if (sci_port->irqs[1] < 0) in sci_init_single()
3015 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) in sci_init_single()
3016 sci_port->irqs[i] = sci_port->irqs[0]; in sci_init_single()
3018 sci_port->params = sci_probe_regmap(p); in sci_init_single()
3019 if (unlikely(sci_port->params == NULL)) in sci_init_single()
3020 return -EINVAL; in sci_init_single()
3022 switch (p->type) { in sci_init_single()
3024 sci_port->rx_trigger = 48; in sci_init_single()
3027 sci_port->rx_trigger = 64; in sci_init_single()
3030 sci_port->rx_trigger = 32; in sci_init_single()
3033 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) in sci_init_single()
3035 sci_port->rx_trigger = 1; in sci_init_single()
3037 sci_port->rx_trigger = 8; in sci_init_single()
3040 sci_port->rx_trigger = 1; in sci_init_single()
3044 sci_port->rx_fifo_timeout = 0; in sci_init_single()
3045 sci_port->hscif_tot = 0; in sci_init_single()
3051 sci_port->sampling_rate_mask = p->sampling_rate in sci_init_single()
3052 ? SCI_SR(p->sampling_rate) in sci_init_single()
3053 : sci_port->params->sampling_rate_mask; in sci_init_single()
3056 ret = sci_init_clocks(sci_port, &dev->dev); in sci_init_single()
3060 port->dev = &dev->dev; in sci_init_single()
3062 pm_runtime_enable(&dev->dev); in sci_init_single()
3065 port->type = p->type; in sci_init_single()
3066 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; in sci_init_single()
3067 port->fifosize = sci_port->params->fifosize; in sci_init_single()
3069 if (port->type == PORT_SCI && !dev->dev.of_node) { in sci_init_single()
3070 if (sci_port->reg_size >= 0x20) in sci_init_single()
3071 port->regshift = 2; in sci_init_single()
3073 port->regshift = 1; in sci_init_single()
3078 * for the multi-IRQ ports, which is where we are primarily in sci_init_single()
3083 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; in sci_init_single()
3084 port->irqflags = 0; in sci_init_single()
3091 pm_runtime_disable(port->port.dev); in sci_cleanup_single()
3108 struct sci_port *sci_port = &sci_ports[co->index]; in serial_console_write()
3109 struct uart_port *port = &sci_port->port; in serial_console_write()
3114 if (port->sysrq) in serial_console_write()
3124 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | in serial_console_write()
3126 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); in serial_console_write()
3155 if (co->index < 0 || co->index >= SCI_NPORTS) in serial_console_setup()
3156 return -ENODEV; in serial_console_setup()
3158 sci_port = &sci_ports[co->index]; in serial_console_setup()
3159 port = &sci_port->port; in serial_console_setup()
3164 if (!port->ops) in serial_console_setup()
3165 return -ENODEV; in serial_console_setup()
3183 .index = -1,
3208 .index = -1,
3213 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); in sci_probe_earlyprintk()
3216 return -EEXIST; in sci_probe_earlyprintk()
3218 early_serial_console.index = pdev->id; in sci_probe_earlyprintk()
3220 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); in sci_probe_earlyprintk()
3235 return -EINVAL; in sci_probe_earlyprintk()
3258 unsigned int type = port->port.type; /* uart_remove_... clears it */ in sci_remove()
3260 sci_ports_in_use &= ~BIT(port->port.line); in sci_remove()
3261 uart_remove_one_port(&sci_uart_driver, &port->port); in sci_remove()
3265 if (port->port.fifosize > 1) in sci_remove()
3266 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_remove()
3268 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_remove()
3277 /* SoC-specific types */
3279 .compatible = "renesas,scif-r7s72100",
3283 .compatible = "renesas,scif-r7s9210",
3287 .compatible = "renesas,scif-r9a07g044",
3291 .compatible = "renesas,scif-r9a09g057",
3294 /* Family-specific types */
3296 .compatible = "renesas,rcar-gen1-scif",
3299 .compatible = "renesas,rcar-gen2-scif",
3302 .compatible = "renesas,rcar-gen3-scif",
3305 .compatible = "renesas,rcar-gen4-scif",
3338 struct device_node *np = pdev->dev.of_node; in sci_parse_dt()
3346 return ERR_PTR(-EINVAL); in sci_parse_dt()
3348 data = of_device_get_match_data(&pdev->dev); in sci_parse_dt()
3350 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in sci_parse_dt()
3352 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), in sci_parse_dt()
3357 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); in sci_parse_dt()
3361 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); in sci_parse_dt()
3363 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", in sci_parse_dt()
3368 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); in sci_parse_dt()
3370 return ERR_PTR(-ENOMEM); in sci_parse_dt()
3377 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); in sci_parse_dt()
3378 return ERR_PTR(-EINVAL); in sci_parse_dt()
3381 dev_err(&pdev->dev, "serial%d out of range\n", id); in sci_parse_dt()
3382 return ERR_PTR(-EINVAL); in sci_parse_dt()
3388 p->type = SCI_OF_TYPE(data); in sci_parse_dt()
3389 p->regtype = SCI_OF_REGTYPE(data); in sci_parse_dt()
3391 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); in sci_parse_dt()
3405 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", in sci_probe_single()
3407 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); in sci_probe_single()
3408 return -EINVAL; in sci_probe_single()
3412 return -EBUSY; in sci_probe_single()
3428 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); in sci_probe_single()
3429 if (IS_ERR(sciport->gpios)) in sci_probe_single()
3430 return PTR_ERR(sciport->gpios); in sci_probe_single()
3432 if (sciport->has_rtscts) { in sci_probe_single()
3433 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || in sci_probe_single()
3434 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { in sci_probe_single()
3435 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); in sci_probe_single()
3436 return -EINVAL; in sci_probe_single()
3438 sciport->port.flags |= UPF_HARD_FLOW; in sci_probe_single()
3441 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); in sci_probe_single()
3467 if (dev->dev.of_node) { in sci_probe()
3472 p = dev->dev.platform_data; in sci_probe()
3474 dev_err(&dev->dev, "no platform data supplied\n"); in sci_probe()
3475 return -EINVAL; in sci_probe()
3478 dev_id = dev->id; in sci_probe()
3488 if (sp->port.fifosize > 1) { in sci_probe()
3489 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_probe()
3493 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || in sci_probe()
3494 sp->port.type == PORT_HSCIF) { in sci_probe()
3495 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_probe()
3497 if (sp->port.fifosize > 1) { in sci_probe()
3498 device_remove_file(&dev->dev, in sci_probe()
3518 uart_suspend_port(&sci_uart_driver, &sport->port); in sci_suspend()
3528 uart_resume_port(&sci_uart_driver, &sport->port); in sci_resume()
3539 .name = "sh-sci",
3570 if (!device->port.membase) in early_console_setup()
3571 return -ENODEV; in early_console_setup()
3573 device->port.type = type; in early_console_setup()
3574 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); in early_console_setup()
3582 device->con->write = serial_console_write; in early_console_setup()
3627 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3628 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3629 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3639 MODULE_ALIAS("platform:sh-sci");