Lines Matching +full:ctrl +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
26 #include <linux/dma-mapping.h>
58 #include "sh-sci.h"
60 /* Offsets into the sci_port->irqs array */
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
125 struct mctrl_gpios *gpios; member
271 * Common SH-2(A) SCIF definitions for ports with FIFO data
326 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
327 * TEI-DRI, RXI-EDGE and TXI-EDGE.
328 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
329 * - SCFCR register does not have SCFCR_MCE bit.
330 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
355 * Common SH-3 SCIF definitions.
377 * Common SH-4(A) SCIF(B) definitions.
457 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
481 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
508 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
531 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
543 if (reg->size == 8) in sci_serial_in()
544 return ioread8(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
545 else if (reg->size == 16) in sci_serial_in()
546 return ioread16(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
557 if (reg->size == 8) in sci_serial_out()
558 iowrite8(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
559 else if (reg->size == 16) in sci_serial_out()
560 iowrite16(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
569 if (!sci_port->port.dev) in sci_port_enable()
572 pm_runtime_get_sync(sci_port->port.dev); in sci_port_enable()
575 clk_prepare_enable(sci_port->clks[i]); in sci_port_enable()
576 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); in sci_port_enable()
578 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; in sci_port_enable()
585 if (!sci_port->port.dev) in sci_port_disable()
588 for (i = SCI_NUM_CLKS; i-- > 0; ) in sci_port_disable()
589 clk_disable_unprepare(sci_port->clks[i]); in sci_port_disable()
591 pm_runtime_put_sync(sci_port->port.dev); in sci_port_disable()
598 * special-casing the port type, we check the port initialization in port_rx_irq_mask()
603 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); in port_rx_irq_mask()
609 unsigned short ctrl; in sci_start_tx() local
612 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
614 if (s->chan_tx) in sci_start_tx()
622 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && in sci_start_tx()
623 dma_submit_error(s->cookie_tx)) { in sci_start_tx()
624 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_start_tx()
626 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); in sci_start_tx()
628 s->cookie_tx = 0; in sci_start_tx()
629 schedule_work(&s->work_tx); in sci_start_tx()
633 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || in sci_start_tx()
634 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
636 ctrl = sci_serial_in(port, SCSCR); in sci_start_tx()
643 if (port->type == PORT_SCI) in sci_start_tx()
644 ctrl |= SCSCR_TE; in sci_start_tx()
646 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); in sci_start_tx()
652 unsigned short ctrl; in sci_stop_tx() local
655 ctrl = sci_serial_in(port, SCSCR); in sci_stop_tx()
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_tx()
658 ctrl &= ~SCSCR_TDRQE; in sci_stop_tx()
660 ctrl &= ~SCSCR_TIE; in sci_stop_tx()
662 sci_serial_out(port, SCSCR, ctrl); in sci_stop_tx()
665 if (to_sci_port(port)->chan_tx && in sci_stop_tx()
666 !dma_submit_error(to_sci_port(port)->cookie_tx)) { in sci_stop_tx()
667 dmaengine_terminate_async(to_sci_port(port)->chan_tx); in sci_stop_tx()
668 to_sci_port(port)->cookie_tx = -EINVAL; in sci_stop_tx()
675 unsigned short ctrl; in sci_start_rx() local
677 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); in sci_start_rx()
679 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_start_rx()
680 ctrl &= ~SCSCR_RDRQE; in sci_start_rx()
682 sci_serial_out(port, SCSCR, ctrl); in sci_start_rx()
687 unsigned short ctrl; in sci_stop_rx() local
689 ctrl = sci_serial_in(port, SCSCR); in sci_stop_rx()
691 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_rx()
692 ctrl &= ~SCSCR_RDRQE; in sci_stop_rx()
694 ctrl &= ~port_rx_irq_mask(port); in sci_stop_rx()
696 sci_serial_out(port, SCSCR, ctrl); in sci_stop_rx()
701 if (port->type == PORT_SCI) { in sci_clear_SCxSR()
704 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { in sci_clear_SCxSR()
764 * Use port-specific handler if provided. in sci_init_pins()
766 if (s->cfg->ops && s->cfg->ops->init_pins) { in sci_init_pins()
767 s->cfg->ops->init_pins(port, cflag); in sci_init_pins()
771 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_init_pins()
773 u16 ctrl = sci_serial_in(port, SCPCR); in sci_init_pins() local
776 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); in sci_init_pins()
777 if (to_sci_port(port)->has_rtscts) { in sci_init_pins()
779 if (!(port->mctrl & TIOCM_RTS)) { in sci_init_pins()
780 ctrl |= SCPCR_RTSC; in sci_init_pins()
782 } else if (!s->autorts) { in sci_init_pins()
783 ctrl |= SCPCR_RTSC; in sci_init_pins()
787 ctrl &= ~SCPCR_RTSC; in sci_init_pins()
790 ctrl &= ~SCPCR_CTSC; in sci_init_pins()
793 sci_serial_out(port, SCPCR, ctrl); in sci_init_pins()
794 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { in sci_init_pins()
799 if (!(port->mctrl & TIOCM_RTS)) in sci_init_pins()
801 else if (!s->autorts) in sci_init_pins()
812 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_txfill()
816 if (reg->size) in sci_txfill()
820 if (reg->size) in sci_txfill()
828 return port->fifosize - sci_txfill(port); in sci_txroom()
834 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_rxfill()
838 if (reg->size) in sci_rxfill()
842 if (reg->size) in sci_rxfill()
854 struct tty_port *tport = &port->state->port; in sci_transmit_chars()
858 unsigned short ctrl; in sci_transmit_chars() local
863 ctrl = sci_serial_in(port, SCSCR); in sci_transmit_chars()
864 if (kfifo_is_empty(&tport->xmit_fifo)) in sci_transmit_chars()
865 ctrl &= ~SCSCR_TIE; in sci_transmit_chars()
867 ctrl |= SCSCR_TIE; in sci_transmit_chars()
868 sci_serial_out(port, SCSCR, ctrl); in sci_transmit_chars()
877 if (port->x_char) { in sci_transmit_chars()
878 c = port->x_char; in sci_transmit_chars()
879 port->x_char = 0; in sci_transmit_chars()
880 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { in sci_transmit_chars()
881 if (port->type == PORT_SCI && in sci_transmit_chars()
882 kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
883 ctrl = sci_serial_in(port, SCSCR); in sci_transmit_chars()
884 ctrl &= ~SCSCR_TE; in sci_transmit_chars()
885 sci_serial_out(port, SCSCR, ctrl); in sci_transmit_chars()
892 s->tx_occurred = true; in sci_transmit_chars()
894 port->icount.tx++; in sci_transmit_chars()
895 } while (--count > 0); in sci_transmit_chars()
899 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_transmit_chars()
901 if (kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
902 if (port->type == PORT_SCI) { in sci_transmit_chars()
903 ctrl = sci_serial_in(port, SCSCR); in sci_transmit_chars()
904 ctrl &= ~SCSCR_TIE; in sci_transmit_chars()
905 ctrl |= SCSCR_TEIE; in sci_transmit_chars()
906 sci_serial_out(port, SCSCR, ctrl); in sci_transmit_chars()
915 struct tty_port *tport = &port->state->port; in sci_receive_chars()
932 if (port->type == PORT_SCI) { in sci_receive_chars()
942 if (port->type == PORT_SCIF || in sci_receive_chars()
943 port->type == PORT_HSCIF) { in sci_receive_chars()
951 count--; i--; in sci_receive_chars()
958 port->icount.frame++; in sci_receive_chars()
961 port->icount.parity++; in sci_receive_chars()
973 port->icount.rx += count; in sci_receive_chars()
991 struct tty_port *tport = &port->state->port; in sci_handle_errors()
995 if (status & s->params->overrun_mask) { in sci_handle_errors()
996 port->icount.overrun++; in sci_handle_errors()
1005 port->icount.frame++; in sci_handle_errors()
1013 port->icount.parity++; in sci_handle_errors()
1027 struct tty_port *tport = &port->state->port; in sci_handle_fifo_overrun()
1033 reg = sci_getreg(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1034 if (!reg->size) in sci_handle_fifo_overrun()
1037 status = sci_serial_in(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1038 if (status & s->params->overrun_mask) { in sci_handle_fifo_overrun()
1039 status &= ~s->params->overrun_mask; in sci_handle_fifo_overrun()
1040 sci_serial_out(port, s->params->overrun_reg, status); in sci_handle_fifo_overrun()
1042 port->icount.overrun++; in sci_handle_fifo_overrun()
1056 struct tty_port *tport = &port->state->port; in sci_handle_breaks()
1062 port->icount.brk++; in sci_handle_breaks()
1081 if (rx_trig >= port->fifosize) in scif_set_rtrg()
1082 rx_trig = port->fifosize - 1; in scif_set_rtrg()
1087 if (sci_getreg(port, HSRTRGR)->size) { in scif_set_rtrg()
1092 switch (port->type) { in scif_set_rtrg()
1138 if (sci_getreg(port, HSRTRGR)->size) in scif_rtrg_enabled()
1148 struct uart_port *port = &s->port; in rx_fifo_timer_fn()
1150 dev_dbg(port->dev, "Rx timed out\n"); in rx_fifo_timer_fn()
1160 return sprintf(buf, "%d\n", sci->rx_trigger); in rx_fifo_trigger_show()
1176 sci->rx_trigger = scif_set_rtrg(port, r); in rx_fifo_trigger_store()
1177 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in rx_fifo_trigger_store()
1193 if (port->type == PORT_HSCIF) in rx_fifo_timeout_show()
1194 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; in rx_fifo_timeout_show()
1196 v = sci->rx_fifo_timeout; in rx_fifo_timeout_show()
1215 if (port->type == PORT_HSCIF) { in rx_fifo_timeout_store()
1217 return -EINVAL; in rx_fifo_timeout_store()
1218 sci->hscif_tot = r << HSSCR_TOT_SHIFT; in rx_fifo_timeout_store()
1220 sci->rx_fifo_timeout = r; in rx_fifo_timeout_store()
1223 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); in rx_fifo_timeout_store()
1236 struct uart_port *port = &s->port; in sci_dma_tx_complete()
1237 struct tty_port *tport = &port->state->port; in sci_dma_tx_complete()
1240 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_dma_tx_complete()
1244 uart_xmit_advance(port, s->tx_dma_len); in sci_dma_tx_complete()
1246 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_dma_tx_complete()
1249 s->tx_occurred = true; in sci_dma_tx_complete()
1251 if (!kfifo_is_empty(&tport->xmit_fifo)) { in sci_dma_tx_complete()
1252 s->cookie_tx = 0; in sci_dma_tx_complete()
1253 schedule_work(&s->work_tx); in sci_dma_tx_complete()
1255 s->cookie_tx = -EINVAL; in sci_dma_tx_complete()
1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_tx_complete()
1257 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1258 u16 ctrl = sci_serial_in(port, SCSCR); in sci_dma_tx_complete() local
1259 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); in sci_dma_tx_complete()
1260 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1262 dmaengine_pause(s->chan_tx_saved); in sci_dma_tx_complete()
1263 enable_irq(s->irqs[SCIx_TXI_IRQ]); in sci_dma_tx_complete()
1274 struct uart_port *port = &s->port; in sci_dma_rx_push()
1275 struct tty_port *tport = &port->state->port; in sci_dma_rx_push()
1280 port->icount.buf_overrun++; in sci_dma_rx_push()
1282 port->icount.rx += copied; in sci_dma_rx_push()
1291 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_find_active()
1292 if (s->active_rx == s->cookie_rx[i]) in sci_dma_rx_find_active()
1295 return -1; in sci_dma_rx_find_active()
1303 s->chan_rx = NULL; in sci_dma_rx_chan_invalidate()
1304 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_chan_invalidate()
1305 s->cookie_rx[i] = -EINVAL; in sci_dma_rx_chan_invalidate()
1306 s->active_rx = 0; in sci_dma_rx_chan_invalidate()
1311 struct dma_chan *chan = s->chan_rx_saved; in sci_dma_rx_release()
1312 struct uart_port *port = &s->port; in sci_dma_rx_release()
1316 s->chan_rx_saved = NULL; in sci_dma_rx_release()
1321 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], in sci_dma_rx_release()
1322 sg_dma_address(&s->sg_rx[0])); in sci_dma_rx_release()
1337 struct uart_port *port = &s->port; in sci_dma_rx_reenable_irq()
1342 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_reenable_irq()
1343 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_rx_reenable_irq()
1344 enable_irq(s->irqs[SCIx_RXI_IRQ]); in sci_dma_rx_reenable_irq()
1345 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_reenable_irq()
1346 scif_set_rtrg(port, s->rx_trigger); in sci_dma_rx_reenable_irq()
1356 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_complete()
1357 struct uart_port *port = &s->port; in sci_dma_rx_complete()
1362 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, in sci_dma_rx_complete()
1363 s->active_rx); in sci_dma_rx_complete()
1365 hrtimer_cancel(&s->rx_timer); in sci_dma_rx_complete()
1371 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); in sci_dma_rx_complete()
1374 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_complete()
1376 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, in sci_dma_rx_complete()
1382 desc->callback = sci_dma_rx_complete; in sci_dma_rx_complete()
1383 desc->callback_param = s; in sci_dma_rx_complete()
1384 s->cookie_rx[active] = dmaengine_submit(desc); in sci_dma_rx_complete()
1385 if (dma_submit_error(s->cookie_rx[active])) in sci_dma_rx_complete()
1388 s->active_rx = s->cookie_rx[!active]; in sci_dma_rx_complete()
1393 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", in sci_dma_rx_complete()
1394 __func__, s->cookie_rx[active], active, s->active_rx); in sci_dma_rx_complete()
1396 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_dma_rx_complete()
1406 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); in sci_dma_rx_complete()
1411 struct dma_chan *chan = s->chan_tx_saved; in sci_dma_tx_release()
1413 cancel_work_sync(&s->work_tx); in sci_dma_tx_release()
1414 s->chan_tx_saved = s->chan_tx = NULL; in sci_dma_tx_release()
1415 s->cookie_tx = -EINVAL; in sci_dma_tx_release()
1417 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, in sci_dma_tx_release()
1424 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_submit()
1425 struct uart_port *port = &s->port; in sci_dma_rx_submit()
1430 struct scatterlist *sg = &s->sg_rx[i]; in sci_dma_rx_submit()
1439 desc->callback = sci_dma_rx_complete; in sci_dma_rx_submit()
1440 desc->callback_param = s; in sci_dma_rx_submit()
1441 s->cookie_rx[i] = dmaengine_submit(desc); in sci_dma_rx_submit()
1442 if (dma_submit_error(s->cookie_rx[i])) in sci_dma_rx_submit()
1447 s->active_rx = s->cookie_rx[0]; in sci_dma_rx_submit()
1462 return -EAGAIN; in sci_dma_rx_submit()
1469 struct dma_chan *chan = s->chan_tx; in sci_dma_tx_work_fn()
1470 struct uart_port *port = &s->port; in sci_dma_tx_work_fn()
1471 struct tty_port *tport = &port->state->port; in sci_dma_tx_work_fn()
1484 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, in sci_dma_tx_work_fn()
1486 buf = s->tx_dma_addr + tail; in sci_dma_tx_work_fn()
1487 if (!s->tx_dma_len) { in sci_dma_tx_work_fn()
1493 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1498 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1502 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1505 desc->callback = sci_dma_tx_complete; in sci_dma_tx_work_fn()
1506 desc->callback_param = s; in sci_dma_tx_work_fn()
1507 s->cookie_tx = dmaengine_submit(desc); in sci_dma_tx_work_fn()
1508 if (dma_submit_error(s->cookie_tx)) { in sci_dma_tx_work_fn()
1510 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1515 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", in sci_dma_tx_work_fn()
1516 __func__, tport->xmit_buf, tail, s->cookie_tx); in sci_dma_tx_work_fn()
1523 s->chan_tx = NULL; in sci_dma_tx_work_fn()
1532 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_timer_fn()
1533 struct uart_port *port = &s->port; in sci_dma_rx_timer_fn()
1540 dev_dbg(port->dev, "DMA Rx timed out\n"); in sci_dma_rx_timer_fn()
1550 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1553 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", in sci_dma_rx_timer_fn()
1554 s->active_rx, active); in sci_dma_rx_timer_fn()
1568 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1571 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); in sci_dma_rx_timer_fn()
1576 dmaengine_terminate_async(s->chan_rx); in sci_dma_rx_timer_fn()
1577 read = sg_dma_len(&s->sg_rx[active]) - state.residue; in sci_dma_rx_timer_fn()
1580 count = sci_dma_rx_push(s, s->rx_buf[active], read); in sci_dma_rx_timer_fn()
1582 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_timer_fn()
1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_timer_fn()
1586 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_timer_fn()
1603 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); in sci_request_dma_chan()
1605 dev_dbg(port->dev, "dma_request_chan failed\n"); in sci_request_dma_chan()
1611 cfg.dst_addr = port->mapbase + in sci_request_dma_chan()
1612 (sci_getreg(port, SCxTDR)->offset << port->regshift); in sci_request_dma_chan()
1614 cfg.src_addr = port->mapbase + in sci_request_dma_chan()
1615 (sci_getreg(port, SCxRDR)->offset << port->regshift); in sci_request_dma_chan()
1620 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); in sci_request_dma_chan()
1631 struct tty_port *tport = &port->state->port; in sci_request_dma()
1634 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); in sci_request_dma()
1643 if (!port->dev->of_node) in sci_request_dma()
1646 s->cookie_tx = -EINVAL; in sci_request_dma()
1652 if (!of_property_present(port->dev->of_node, "dmas")) in sci_request_dma()
1656 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); in sci_request_dma()
1659 s->tx_dma_addr = dma_map_single(chan->device->dev, in sci_request_dma()
1660 tport->xmit_buf, in sci_request_dma()
1663 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { in sci_request_dma()
1664 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); in sci_request_dma()
1667 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", in sci_request_dma()
1669 tport->xmit_buf, &s->tx_dma_addr); in sci_request_dma()
1671 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); in sci_request_dma()
1672 s->chan_tx_saved = s->chan_tx = chan; in sci_request_dma()
1677 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); in sci_request_dma()
1683 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); in sci_request_dma()
1684 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, in sci_request_dma()
1687 dev_warn(port->dev, in sci_request_dma()
1694 struct scatterlist *sg = &s->sg_rx[i]; in sci_request_dma()
1697 s->rx_buf[i] = buf; in sci_request_dma()
1699 sg_dma_len(sg) = s->buf_len_rx; in sci_request_dma()
1701 buf += s->buf_len_rx; in sci_request_dma()
1702 dma += s->buf_len_rx; in sci_request_dma()
1705 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in sci_request_dma()
1706 s->rx_timer.function = sci_dma_rx_timer_fn; in sci_request_dma()
1708 s->chan_rx_saved = s->chan_rx = chan; in sci_request_dma()
1710 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_request_dma()
1711 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_request_dma()
1720 if (s->chan_tx_saved) in sci_free_dma()
1722 if (s->chan_rx_saved) in sci_free_dma()
1735 s->tx_dma_len = 0; in sci_flush_buffer()
1736 if (s->chan_tx) { in sci_flush_buffer()
1737 dmaengine_terminate_async(s->chan_tx); in sci_flush_buffer()
1738 s->cookie_tx = -EINVAL; in sci_flush_buffer()
1747 if (!s->chan_tx) in sci_dma_check_tx_occurred()
1750 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); in sci_dma_check_tx_occurred()
1752 s->tx_occurred = true; in sci_dma_check_tx_occurred()
1776 if (s->chan_rx) { in sci_rx_interrupt()
1781 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_rx_interrupt()
1782 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1783 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); in sci_rx_interrupt()
1784 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1800 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", in sci_rx_interrupt()
1801 jiffies, s->rx_timeout); in sci_rx_interrupt()
1802 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_rx_interrupt()
1810 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { in sci_rx_interrupt()
1812 scif_set_rtrg(port, s->rx_trigger); in sci_rx_interrupt()
1814 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( in sci_rx_interrupt()
1815 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); in sci_rx_interrupt()
1843 unsigned short ctrl; in sci_tx_end_interrupt() local
1845 if (port->type != PORT_SCI) in sci_tx_end_interrupt()
1849 ctrl = sci_serial_in(port, SCSCR); in sci_tx_end_interrupt()
1850 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); in sci_tx_end_interrupt()
1851 sci_serial_out(port, SCSCR, ctrl); in sci_tx_end_interrupt()
1877 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { in sci_er_interrupt()
1891 if (port->type == PORT_SCI) { in sci_er_interrupt()
1899 if (!s->chan_rx) in sci_er_interrupt()
1906 if (!s->chan_tx) in sci_er_interrupt()
1921 if (s->params->overrun_reg == SCxSR) in sci_mpxed_interrupt()
1923 else if (sci_getreg(port, s->params->overrun_reg)->size) in sci_mpxed_interrupt()
1924 orer_status = sci_serial_in(port, s->params->overrun_reg); in sci_mpxed_interrupt()
1930 !s->chan_tx) in sci_mpxed_interrupt()
1937 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && in sci_mpxed_interrupt()
1946 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && in sci_mpxed_interrupt()
1951 if (orer_status & s->params->overrun_mask) { in sci_mpxed_interrupt()
2007 struct uart_port *up = &port->port; in sci_request_irq()
2016 if (port->irqs[w] == port->irqs[i]) in sci_request_irq()
2023 irq = up->irq; in sci_request_irq()
2025 irq = port->irqs[i]; in sci_request_irq()
2036 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", in sci_request_irq()
2037 dev_name(up->dev), desc->desc); in sci_request_irq()
2038 if (!port->irqstr[j]) { in sci_request_irq()
2039 ret = -ENOMEM; in sci_request_irq()
2043 ret = request_irq(irq, desc->handler, up->irqflags, in sci_request_irq()
2044 port->irqstr[j], port); in sci_request_irq()
2046 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); in sci_request_irq()
2054 while (--i >= 0) in sci_request_irq()
2055 free_irq(port->irqs[i], port); in sci_request_irq()
2058 while (--j >= 0) in sci_request_irq()
2059 kfree(port->irqstr[j]); in sci_request_irq()
2073 int irq = port->irqs[i]; in sci_free_irq()
2084 if (port->irqs[j] == irq) in sci_free_irq()
2089 free_irq(port->irqs[i], port); in sci_free_irq()
2090 kfree(port->irqstr[i]); in sci_free_irq()
2107 if (!s->tx_occurred) in sci_tx_empty()
2115 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_rts()
2128 } else if (sci_getreg(port, SCSPTR)->size) { in sci_set_rts()
2129 u16 ctrl = sci_serial_in(port, SCSPTR); in sci_set_rts() local
2133 ctrl &= ~SCSPTR_RTSDT; in sci_set_rts()
2135 ctrl |= SCSPTR_RTSDT; in sci_set_rts()
2136 sci_serial_out(port, SCSPTR, ctrl); in sci_set_rts()
2142 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_get_cts()
2145 } else if (sci_getreg(port, SCSPTR)->size) { in sci_get_cts()
2157 * handled via the ->init_pins() op, which is a bit of a one-way street,
2158 * lacking any ability to defer pin control -- this will later be
2176 if (reg->size) in sci_set_mctrl()
2181 mctrl_gpio_set(s->gpios, mctrl); in sci_set_mctrl()
2183 if (!s->has_rtscts) in sci_set_mctrl()
2188 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2194 } else if (s->autorts) { in sci_set_mctrl()
2195 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_mctrl()
2202 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2214 struct mctrl_gpios *gpios = s->gpios; in sci_get_mctrl() local
2217 mctrl_gpio_get(gpios, &mctrl); in sci_get_mctrl()
2223 if (s->autorts) { in sci_get_mctrl()
2226 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { in sci_get_mctrl()
2229 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) in sci_get_mctrl()
2231 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) in sci_get_mctrl()
2239 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); in sci_enable_ms()
2248 if (!sci_getreg(port, SCSPTR)->size) { in sci_break_ctl()
2260 if (break_state == -1) { in sci_break_ctl()
2278 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_startup()
2280 s->tx_occurred = false; in sci_startup()
2298 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_shutdown()
2300 s->autorts = false; in sci_shutdown()
2301 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); in sci_shutdown()
2312 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); in sci_shutdown()
2316 if (s->chan_rx_saved) { in sci_shutdown()
2317 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, in sci_shutdown()
2318 port->line); in sci_shutdown()
2319 hrtimer_cancel(&s->rx_timer); in sci_shutdown()
2323 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) in sci_shutdown()
2324 del_timer_sync(&s->rx_fifo_timer); in sci_shutdown()
2332 unsigned long freq = s->clk_rates[SCI_SCK]; in sci_sck_calc()
2336 if (s->port.type != PORT_HSCIF) in sci_sck_calc()
2340 err = DIV_ROUND_CLOSEST(freq, sr) - bps; in sci_sck_calc()
2345 *srr = sr - 1; in sci_sck_calc()
2351 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, in sci_sck_calc()
2363 if (s->port.type != PORT_HSCIF) in sci_brg_calc()
2370 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; in sci_brg_calc()
2376 *srr = sr - 1; in sci_brg_calc()
2382 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, in sci_brg_calc()
2392 unsigned long freq = s->clk_rates[SCI_FCK]; in sci_scbrr_calc()
2396 if (s->port.type != PORT_HSCIF) in sci_scbrr_calc()
2410 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - in sci_scbrr_calc()
2411 * (|D - 0.5| / N * (1 + F))| in sci_scbrr_calc()
2423 * err = freq / (br * prediv) - bps in sci_scbrr_calc()
2435 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
2440 *brr = br - 1; in sci_scbrr_calc()
2441 *srr = sr - 1; in sci_scbrr_calc()
2450 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, in sci_scbrr_calc()
2461 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ in sci_reset()
2464 if (reg->size) in sci_reset()
2470 if (sci_getreg(port, SCLSR)->size) { in sci_reset()
2476 if (s->rx_trigger > 1) { in sci_reset()
2477 if (s->rx_fifo_timeout) { in sci_reset()
2479 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); in sci_reset()
2481 if (port->type == PORT_SCIFA || in sci_reset()
2482 port->type == PORT_SCIFB) in sci_reset()
2485 scif_set_rtrg(port, s->rx_trigger); in sci_reset()
2500 int best_clk = -1; in sci_set_termios()
2503 if ((termios->c_cflag & CSIZE) == CS7) { in sci_set_termios()
2506 termios->c_cflag &= ~CSIZE; in sci_set_termios()
2507 termios->c_cflag |= CS8; in sci_set_termios()
2509 if (termios->c_cflag & PARENB) in sci_set_termios()
2511 if (termios->c_cflag & PARODD) in sci_set_termios()
2513 if (termios->c_cflag & CSTOPB) in sci_set_termios()
2517 * earlyprintk comes here early on with port->uartclk set to zero. in sci_set_termios()
2520 * the baud rate is not programmed during earlyprintk - it is assumed in sci_set_termios()
2524 if (!port->uartclk) { in sci_set_termios()
2530 max_freq = max(max_freq, s->clk_rates[i]); in sci_set_termios()
2542 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && in sci_set_termios()
2543 port->type != PORT_SCIFB) { in sci_set_termios()
2557 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2558 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, in sci_set_termios()
2573 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2574 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, in sci_set_termios()
2601 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", in sci_set_termios()
2602 s->clks[best_clk], baud, min_err); in sci_set_termios()
2610 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { in sci_set_termios()
2619 uart_update_timeout(port, termios->c_cflag, baud); in sci_set_termios()
2622 bits = tty_get_frame_size(termios->c_cflag); in sci_set_termios()
2624 if (sci_getreg(port, SEMR)->size) in sci_set_termios()
2628 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_set_termios()
2640 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2643 if (sci_getreg(port, HSSRR)->size) { in sci_set_termios()
2648 int last_stop = bits * 2 - 1; in sci_set_termios()
2658 int shift = clamp(deviation / 2, -8, 7); in sci_set_termios()
2668 udelay((1000000 + (baud - 1)) / baud); in sci_set_termios()
2671 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); in sci_set_termios()
2674 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2678 sci_init_pins(port, termios->c_cflag); in sci_set_termios()
2680 port->status &= ~UPSTAT_AUTOCTS; in sci_set_termios()
2681 s->autorts = false; in sci_set_termios()
2683 if (reg->size) { in sci_set_termios()
2684 unsigned short ctrl = sci_serial_in(port, SCFCR); in sci_set_termios() local
2686 if ((port->flags & UPF_HARD_FLOW) && in sci_set_termios()
2687 (termios->c_cflag & CRTSCTS)) { in sci_set_termios()
2689 port->status |= UPSTAT_AUTOCTS; in sci_set_termios()
2691 s->autorts = true; in sci_set_termios()
2699 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); in sci_set_termios()
2701 sci_serial_out(port, SCFCR, ctrl); in sci_set_termios()
2703 if (port->flags & UPF_HARD_FLOW) { in sci_set_termios()
2705 sci_set_mctrl(port, port->mctrl); in sci_set_termios()
2713 if (port->type != PORT_SCI) in sci_set_termios()
2715 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); in sci_set_termios()
2716 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2718 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { in sci_set_termios()
2729 s->rx_frame = (10000 * bits) / (baud / 100); in sci_set_termios()
2731 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; in sci_set_termios()
2734 if ((termios->c_cflag & CREAD) != 0) in sci_set_termios()
2741 if (UART_ENABLE_MS(port, termios->c_cflag)) in sci_set_termios()
2762 switch (port->type) { in sci_type()
2787 if (port->membase) in sci_remap_port()
2790 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_remap_port()
2791 port->membase = ioremap(port->mapbase, sport->reg_size); in sci_remap_port()
2792 if (unlikely(!port->membase)) { in sci_remap_port()
2793 dev_err(port->dev, "can't remap port#%d\n", port->line); in sci_remap_port()
2794 return -ENXIO; in sci_remap_port()
2802 port->membase = (void __iomem *)(uintptr_t)port->mapbase; in sci_remap_port()
2812 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_release_port()
2813 iounmap(port->membase); in sci_release_port()
2814 port->membase = NULL; in sci_release_port()
2817 release_mem_region(port->mapbase, sport->reg_size); in sci_release_port()
2826 res = request_mem_region(port->mapbase, sport->reg_size, in sci_request_port()
2827 dev_name(port->dev)); in sci_request_port()
2829 dev_err(port->dev, "request_mem_region failed."); in sci_request_port()
2830 return -EBUSY; in sci_request_port()
2847 port->type = sport->cfg->type; in sci_config_port()
2854 if (ser->baud_base < 2400) in sci_verify_port()
2856 return -EINVAL; in sci_verify_port()
2897 if (sci_port->cfg->type == PORT_HSCIF) in sci_init_clocks()
2923 sci_port->clks[i] = clk; in sci_init_clocks()
2933 if (cfg->regtype != SCIx_PROBE_REGTYPE) in sci_probe_regmap()
2934 return &sci_port_params[cfg->regtype]; in sci_probe_regmap()
2936 switch (cfg->type) { in sci_probe_regmap()
2951 * The SH-4 is a bit of a misnomer here, although that's in sci_probe_regmap()
2973 struct uart_port *port = &sci_port->port; in sci_init_single()
2978 sci_port->cfg = p; in sci_init_single()
2980 port->ops = &sci_uart_ops; in sci_init_single()
2981 port->iotype = UPIO_MEM; in sci_init_single()
2982 port->line = index; in sci_init_single()
2983 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); in sci_init_single()
2987 return -ENOMEM; in sci_init_single()
2989 port->mapbase = res->start; in sci_init_single()
2990 sci_port->reg_size = resource_size(res); in sci_init_single()
2992 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { in sci_init_single()
2994 sci_port->irqs[i] = platform_get_irq_optional(dev, i); in sci_init_single()
2996 sci_port->irqs[i] = platform_get_irq(dev, i); in sci_init_single()
3003 if (p->type == PORT_SCI) in sci_init_single()
3004 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); in sci_init_single()
3009 * In the non-muxed case, up to 6 interrupt signals might be generated in sci_init_single()
3013 if (sci_port->irqs[0] < 0) in sci_init_single()
3014 return -ENXIO; in sci_init_single()
3016 if (sci_port->irqs[1] < 0) in sci_init_single()
3017 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) in sci_init_single()
3018 sci_port->irqs[i] = sci_port->irqs[0]; in sci_init_single()
3020 sci_port->params = sci_probe_regmap(p); in sci_init_single()
3021 if (unlikely(sci_port->params == NULL)) in sci_init_single()
3022 return -EINVAL; in sci_init_single()
3024 switch (p->type) { in sci_init_single()
3026 sci_port->rx_trigger = 48; in sci_init_single()
3029 sci_port->rx_trigger = 64; in sci_init_single()
3032 sci_port->rx_trigger = 32; in sci_init_single()
3035 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) in sci_init_single()
3037 sci_port->rx_trigger = 1; in sci_init_single()
3039 sci_port->rx_trigger = 8; in sci_init_single()
3042 sci_port->rx_trigger = 1; in sci_init_single()
3046 sci_port->rx_fifo_timeout = 0; in sci_init_single()
3047 sci_port->hscif_tot = 0; in sci_init_single()
3053 sci_port->sampling_rate_mask = p->sampling_rate in sci_init_single()
3054 ? SCI_SR(p->sampling_rate) in sci_init_single()
3055 : sci_port->params->sampling_rate_mask; in sci_init_single()
3058 ret = sci_init_clocks(sci_port, &dev->dev); in sci_init_single()
3063 port->type = p->type; in sci_init_single()
3064 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; in sci_init_single()
3065 port->fifosize = sci_port->params->fifosize; in sci_init_single()
3067 if (port->type == PORT_SCI && !dev->dev.of_node) { in sci_init_single()
3068 if (sci_port->reg_size >= 0x20) in sci_init_single()
3069 port->regshift = 2; in sci_init_single()
3071 port->regshift = 1; in sci_init_single()
3076 * for the multi-IRQ ports, which is where we are primarily in sci_init_single()
3081 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; in sci_init_single()
3082 port->irqflags = 0; in sci_init_single()
3101 struct sci_port *sci_port = &sci_ports[co->index]; in serial_console_write()
3102 struct uart_port *port = &sci_port->port; in serial_console_write()
3103 unsigned short bits, ctrl, ctrl_temp; in serial_console_write() local
3107 if (port->sysrq) in serial_console_write()
3115 ctrl = sci_serial_in(port, SCSCR); in serial_console_write()
3117 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | in serial_console_write()
3118 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); in serial_console_write()
3119 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); in serial_console_write()
3129 sci_serial_out(port, SCSCR, ctrl); in serial_console_write()
3148 if (co->index < 0 || co->index >= SCI_NPORTS) in serial_console_setup()
3149 return -ENODEV; in serial_console_setup()
3151 sci_port = &sci_ports[co->index]; in serial_console_setup()
3152 port = &sci_port->port; in serial_console_setup()
3157 if (!port->ops) in serial_console_setup()
3158 return -ENODEV; in serial_console_setup()
3176 .index = -1,
3201 .index = -1,
3206 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); in sci_probe_earlyprintk()
3209 return -EEXIST; in sci_probe_earlyprintk()
3211 early_serial_console.index = pdev->id; in sci_probe_earlyprintk()
3213 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); in sci_probe_earlyprintk()
3228 return -EINVAL; in sci_probe_earlyprintk()
3251 unsigned int type = port->port.type; /* uart_remove_... clears it */ in sci_remove()
3253 sci_ports_in_use &= ~BIT(port->port.line); in sci_remove()
3254 uart_remove_one_port(&sci_uart_driver, &port->port); in sci_remove()
3256 if (port->port.fifosize > 1) in sci_remove()
3257 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_remove()
3259 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_remove()
3268 /* SoC-specific types */
3270 .compatible = "renesas,scif-r7s72100",
3274 .compatible = "renesas,scif-r7s9210",
3278 .compatible = "renesas,scif-r9a07g044",
3282 .compatible = "renesas,scif-r9a09g057",
3285 /* Family-specific types */
3287 .compatible = "renesas,rcar-gen1-scif",
3290 .compatible = "renesas,rcar-gen2-scif",
3293 .compatible = "renesas,rcar-gen3-scif",
3296 .compatible = "renesas,rcar-gen4-scif",
3329 struct device_node *np = pdev->dev.of_node; in sci_parse_dt()
3337 return ERR_PTR(-EINVAL); in sci_parse_dt()
3339 data = of_device_get_match_data(&pdev->dev); in sci_parse_dt()
3341 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in sci_parse_dt()
3343 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), in sci_parse_dt()
3344 "failed to get reset ctrl\n")); in sci_parse_dt()
3348 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); in sci_parse_dt()
3352 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); in sci_parse_dt()
3354 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", in sci_parse_dt()
3359 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); in sci_parse_dt()
3361 return ERR_PTR(-ENOMEM); in sci_parse_dt()
3368 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); in sci_parse_dt()
3369 return ERR_PTR(-EINVAL); in sci_parse_dt()
3372 dev_err(&pdev->dev, "serial%d out of range\n", id); in sci_parse_dt()
3373 return ERR_PTR(-EINVAL); in sci_parse_dt()
3379 p->type = SCI_OF_TYPE(data); in sci_parse_dt()
3380 p->regtype = SCI_OF_REGTYPE(data); in sci_parse_dt()
3382 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); in sci_parse_dt()
3397 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", in sci_probe_single()
3399 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); in sci_probe_single()
3400 return -EINVAL; in sci_probe_single()
3404 return -EBUSY; in sci_probe_single()
3420 sciport->port.dev = &dev->dev; in sci_probe_single()
3421 ret = devm_pm_runtime_enable(&dev->dev); in sci_probe_single()
3425 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); in sci_probe_single()
3426 if (IS_ERR(sciport->gpios)) in sci_probe_single()
3427 return PTR_ERR(sciport->gpios); in sci_probe_single()
3429 if (sciport->has_rtscts) { in sci_probe_single()
3430 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || in sci_probe_single()
3431 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { in sci_probe_single()
3432 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); in sci_probe_single()
3433 return -EINVAL; in sci_probe_single()
3435 sciport->port.flags |= UPF_HARD_FLOW; in sci_probe_single()
3438 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { in sci_probe_single()
3441 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and in sci_probe_single()
3442 * - it now maps to an alias other than zero and in sci_probe_single()
3443 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is in sci_probe_single()
3453 pm_runtime_get_noresume(&dev->dev); in sci_probe_single()
3462 return uart_add_one_port(&sci_uart_driver, &sciport->port); in sci_probe_single()
3483 if (dev->dev.of_node) { in sci_probe()
3488 p = dev->dev.platform_data; in sci_probe()
3490 dev_err(&dev->dev, "no platform data supplied\n"); in sci_probe()
3491 return -EINVAL; in sci_probe()
3494 dev_id = dev->id; in sci_probe()
3501 * - the probed port alias is zero (as the one used by earlycon), and in sci_probe()
3502 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in in sci_probe()
3513 return -ENODEV; in sci_probe()
3515 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) in sci_probe()
3516 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); in sci_probe()
3524 if (sp->port.fifosize > 1) { in sci_probe()
3525 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_probe()
3529 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || in sci_probe()
3530 sp->port.type == PORT_HSCIF) { in sci_probe()
3531 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_probe()
3533 if (sp->port.fifosize > 1) { in sci_probe()
3534 device_remove_file(&dev->dev, in sci_probe()
3554 uart_suspend_port(&sci_uart_driver, &sport->port); in sci_suspend()
3564 uart_resume_port(&sci_uart_driver, &sport->port); in sci_resume()
3575 .name = "sh-sci",
3622 if (!device->port.membase) in early_console_setup()
3623 return -ENODEV; in early_console_setup()
3625 device->port.type = type; in early_console_setup()
3626 sci_ports[0].port = device->port; in early_console_setup()
3635 device->con->write = serial_console_write; in early_console_setup()
3636 device->con->exit = early_console_exit; in early_console_setup()
3682 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3683 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3684 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3694 MODULE_ALIAS("platform:sh-sci");