Lines Matching +full:t1 +full:- +full:framing +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
26 #include <linux/dma-mapping.h>
59 #include "sh-sci.h"
60 #include "sh-sci-common.h"
63 ((port)->irqs[SCIx_ERI_IRQ] == \
64 (port)->irqs[SCIx_RXI_IRQ]) || \
65 ((port)->irqs[SCIx_ERI_IRQ] && \
66 ((port)->irqs[SCIx_RXI_IRQ] < 0))
74 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
75 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
225 * Common SH-2(A) SCIF definitions for ports with FIFO data
252 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
284 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
285 * TEI-DRI, RXI-EDGE and TXI-EDGE.
286 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
287 * - SCFCR register does not have SCFCR_MCE bit.
288 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
315 * Common SH-3 SCIF definitions.
339 * Common SH-4(A) SCIF(B) definitions.
425 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
451 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
480 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
505 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
517 if (reg->size == 8) in sci_serial_in()
518 return ioread8(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
519 else if (reg->size == 16) in sci_serial_in()
520 return ioread16(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
531 if (reg->size == 8) in sci_serial_out()
532 iowrite8(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
533 else if (reg->size == 16) in sci_serial_out()
534 iowrite16(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
543 if (!sci_port->port.dev) in sci_port_enable()
546 pm_runtime_get_sync(sci_port->port.dev); in sci_port_enable()
549 clk_prepare_enable(sci_port->clks[i]); in sci_port_enable()
550 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); in sci_port_enable()
552 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; in sci_port_enable()
560 if (!sci_port->port.dev) in sci_port_disable()
563 for (i = SCI_NUM_CLKS; i-- > 0; ) in sci_port_disable()
564 clk_disable_unprepare(sci_port->clks[i]); in sci_port_disable()
566 pm_runtime_put_sync(sci_port->port.dev); in sci_port_disable()
574 * special-casing the port type, we check the port initialization in port_rx_irq_mask()
579 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); in port_rx_irq_mask()
588 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { in sci_start_tx()
590 if (s->chan_tx) in sci_start_tx()
598 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && in sci_start_tx()
599 dma_submit_error(s->cookie_tx)) { in sci_start_tx()
600 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_start_tx()
602 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); in sci_start_tx()
604 s->cookie_tx = 0; in sci_start_tx()
605 schedule_work(&s->work_tx); in sci_start_tx()
609 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE || in sci_start_tx()
610 s->type == PORT_SCIFA || s->type == PORT_SCIFB) { in sci_start_tx()
619 if (s->type == PORT_SCI) in sci_start_tx()
634 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) in sci_stop_tx()
642 if (s->chan_tx && in sci_stop_tx()
643 !dma_submit_error(s->cookie_tx)) { in sci_stop_tx()
644 dmaengine_terminate_async(s->chan_tx); in sci_stop_tx()
645 s->cookie_tx = -EINVAL; in sci_stop_tx()
657 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) in sci_start_rx()
670 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) in sci_stop_rx()
682 if (s->type == PORT_SCI) { in sci_clear_SCxSR()
685 } else if (s->params->overrun_mask == SCIFA_ORER) { in sci_clear_SCxSR()
690 /* Store the mask, clear parity/framing errors */ in sci_clear_SCxSR()
708 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); in sci_poll_get_char()
721 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); in sci_poll_get_char()
730 const struct sci_common_regs *regs = s->params->common_regs; in sci_poll_put_char()
734 status = s->ops->read_reg(port, regs->status); in sci_poll_put_char()
738 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); in sci_poll_put_char()
748 * Use port-specific handler if provided. in sci_init_pins()
750 if (s->cfg->ops && s->cfg->ops->init_pins) { in sci_init_pins()
751 s->cfg->ops->init_pins(port, cflag); in sci_init_pins()
755 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { in sci_init_pins()
761 if (s->has_rtscts) { in sci_init_pins()
763 if (!(port->mctrl & TIOCM_RTS)) { in sci_init_pins()
766 } else if (!s->autorts) { in sci_init_pins()
778 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) { in sci_init_pins()
783 if (!(port->mctrl & TIOCM_RTS)) in sci_init_pins()
785 else if (!s->autorts) in sci_init_pins()
796 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_txfill()
800 if (reg->size) in sci_txfill()
804 if (reg->size) in sci_txfill()
812 return port->fifosize - sci_txfill(port); in sci_txroom()
818 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_rxfill()
822 if (reg->size) in sci_rxfill()
826 if (reg->size) in sci_rxfill()
838 struct tty_port *tport = &port->state->port; in sci_transmit_chars()
848 if (kfifo_is_empty(&tport->xmit_fifo)) in sci_transmit_chars()
861 if (port->x_char) { in sci_transmit_chars()
862 c = port->x_char; in sci_transmit_chars()
863 port->x_char = 0; in sci_transmit_chars()
864 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { in sci_transmit_chars()
865 if (s->type == PORT_SCI && in sci_transmit_chars()
866 kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
876 s->tx_occurred = true; in sci_transmit_chars()
878 port->icount.tx++; in sci_transmit_chars()
879 } while (--count > 0); in sci_transmit_chars()
881 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); in sci_transmit_chars()
883 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_transmit_chars()
885 if (kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
886 if (s->type == PORT_SCI) { in sci_transmit_chars()
899 struct tty_port *tport = &port->state->port; in sci_receive_chars()
917 if (s->type == PORT_SCI) { in sci_receive_chars()
927 if (s->type == PORT_SCIF || in sci_receive_chars()
928 s->type == PORT_HSCIF) { in sci_receive_chars()
936 count--; i--; in sci_receive_chars()
943 port->icount.frame++; in sci_receive_chars()
946 port->icount.parity++; in sci_receive_chars()
955 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); in sci_receive_chars()
958 port->icount.rx += count; in sci_receive_chars()
968 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); in sci_receive_chars()
976 const struct sci_common_regs *regs = s->params->common_regs; in sci_handle_errors()
977 unsigned int status = s->ops->read_reg(port, regs->status); in sci_handle_errors()
978 struct tty_port *tport = &port->state->port; in sci_handle_errors()
981 if (status & s->params->overrun_mask) { in sci_handle_errors()
982 port->icount.overrun++; in sci_handle_errors()
991 port->icount.frame++; in sci_handle_errors()
999 port->icount.parity++; in sci_handle_errors()
1013 struct tty_port *tport = &port->state->port; in sci_handle_fifo_overrun()
1019 if (s->type != SCI_PORT_RSCI) { in sci_handle_fifo_overrun()
1020 reg = sci_getreg(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1021 if (!reg->size) in sci_handle_fifo_overrun()
1025 status = s->ops->read_reg(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1026 if (status & s->params->overrun_mask) { in sci_handle_fifo_overrun()
1027 status &= ~s->params->overrun_mask; in sci_handle_fifo_overrun()
1028 s->ops->write_reg(port, s->params->overrun_reg, status); in sci_handle_fifo_overrun()
1030 port->icount.overrun++; in sci_handle_fifo_overrun()
1044 struct tty_port *tport = &port->state->port; in sci_handle_breaks()
1050 port->icount.brk++; in sci_handle_breaks()
1070 if (rx_trig >= port->fifosize) in scif_set_rtrg()
1071 rx_trig = port->fifosize - 1; in scif_set_rtrg()
1076 if (sci_getreg(port, HSRTRGR)->size) { in scif_set_rtrg()
1081 switch (s->type) { in scif_set_rtrg()
1127 if (sci_getreg(port, HSRTRGR)->size) in scif_rtrg_enabled()
1137 struct uart_port *port = &s->port; in rx_fifo_timer_fn()
1139 dev_dbg(port->dev, "Rx timed out\n"); in rx_fifo_timer_fn()
1140 s->ops->set_rtrg(port, 1); in rx_fifo_timer_fn()
1149 return sprintf(buf, "%d\n", sci->rx_trigger); in rx_fifo_trigger_show()
1165 sci->rx_trigger = sci->ops->set_rtrg(port, r); in rx_fifo_trigger_store()
1166 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB) in rx_fifo_trigger_store()
1167 sci->ops->set_rtrg(port, 1); in rx_fifo_trigger_store()
1182 if (sci->type == PORT_HSCIF) in rx_fifo_timeout_show()
1183 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; in rx_fifo_timeout_show()
1185 v = sci->rx_fifo_timeout; in rx_fifo_timeout_show()
1204 if (sci->type == PORT_HSCIF) { in rx_fifo_timeout_store()
1206 return -EINVAL; in rx_fifo_timeout_store()
1207 sci->hscif_tot = r << HSSCR_TOT_SHIFT; in rx_fifo_timeout_store()
1209 sci->rx_fifo_timeout = r; in rx_fifo_timeout_store()
1210 sci->ops->set_rtrg(port, 1); in rx_fifo_timeout_store()
1212 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); in rx_fifo_timeout_store()
1225 struct uart_port *port = &s->port; in sci_dma_tx_complete()
1226 struct tty_port *tport = &port->state->port; in sci_dma_tx_complete()
1229 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_dma_tx_complete()
1233 uart_xmit_advance(port, s->tx_dma_len); in sci_dma_tx_complete()
1235 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_dma_tx_complete()
1238 s->tx_occurred = true; in sci_dma_tx_complete()
1240 if (!kfifo_is_empty(&tport->xmit_fifo)) { in sci_dma_tx_complete()
1241 s->cookie_tx = 0; in sci_dma_tx_complete()
1242 schedule_work(&s->work_tx); in sci_dma_tx_complete()
1244 s->cookie_tx = -EINVAL; in sci_dma_tx_complete()
1245 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || in sci_dma_tx_complete()
1246 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1249 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1251 dmaengine_pause(s->chan_tx_saved); in sci_dma_tx_complete()
1252 enable_irq(s->irqs[SCIx_TXI_IRQ]); in sci_dma_tx_complete()
1263 struct uart_port *port = &s->port; in sci_dma_rx_push()
1264 struct tty_port *tport = &port->state->port; in sci_dma_rx_push()
1269 port->icount.buf_overrun++; in sci_dma_rx_push()
1271 port->icount.rx += copied; in sci_dma_rx_push()
1280 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_find_active()
1281 if (s->active_rx == s->cookie_rx[i]) in sci_dma_rx_find_active()
1284 return -1; in sci_dma_rx_find_active()
1292 s->chan_rx = NULL; in sci_dma_rx_chan_invalidate()
1293 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_chan_invalidate()
1294 s->cookie_rx[i] = -EINVAL; in sci_dma_rx_chan_invalidate()
1295 s->active_rx = 0; in sci_dma_rx_chan_invalidate()
1300 struct dma_chan *chan = s->chan_rx_saved; in sci_dma_rx_release()
1301 struct uart_port *port = &s->port; in sci_dma_rx_release()
1305 s->chan_rx_saved = NULL; in sci_dma_rx_release()
1310 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], in sci_dma_rx_release()
1311 sg_dma_address(&s->sg_rx[0])); in sci_dma_rx_release()
1326 struct uart_port *port = &s->port; in sci_dma_rx_reenable_irq()
1331 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || in sci_dma_rx_reenable_irq()
1332 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_rx_reenable_irq()
1333 enable_irq(s->irqs[SCIx_RXI_IRQ]); in sci_dma_rx_reenable_irq()
1334 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_reenable_irq()
1335 s->ops->set_rtrg(port, s->rx_trigger); in sci_dma_rx_reenable_irq()
1345 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_complete()
1346 struct uart_port *port = &s->port; in sci_dma_rx_complete()
1351 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, in sci_dma_rx_complete()
1352 s->active_rx); in sci_dma_rx_complete()
1354 hrtimer_cancel(&s->rx_timer); in sci_dma_rx_complete()
1360 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); in sci_dma_rx_complete()
1363 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_complete()
1365 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, in sci_dma_rx_complete()
1371 desc->callback = sci_dma_rx_complete; in sci_dma_rx_complete()
1372 desc->callback_param = s; in sci_dma_rx_complete()
1373 s->cookie_rx[active] = dmaengine_submit(desc); in sci_dma_rx_complete()
1374 if (dma_submit_error(s->cookie_rx[active])) in sci_dma_rx_complete()
1377 s->active_rx = s->cookie_rx[!active]; in sci_dma_rx_complete()
1382 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", in sci_dma_rx_complete()
1383 __func__, s->cookie_rx[active], active, s->active_rx); in sci_dma_rx_complete()
1385 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_dma_rx_complete()
1395 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); in sci_dma_rx_complete()
1400 struct dma_chan *chan = s->chan_tx_saved; in sci_dma_tx_release()
1402 cancel_work_sync(&s->work_tx); in sci_dma_tx_release()
1403 s->chan_tx_saved = s->chan_tx = NULL; in sci_dma_tx_release()
1404 s->cookie_tx = -EINVAL; in sci_dma_tx_release()
1406 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, in sci_dma_tx_release()
1413 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_submit()
1414 struct uart_port *port = &s->port; in sci_dma_rx_submit()
1419 struct scatterlist *sg = &s->sg_rx[i]; in sci_dma_rx_submit()
1428 desc->callback = sci_dma_rx_complete; in sci_dma_rx_submit()
1429 desc->callback_param = s; in sci_dma_rx_submit()
1430 s->cookie_rx[i] = dmaengine_submit(desc); in sci_dma_rx_submit()
1431 if (dma_submit_error(s->cookie_rx[i])) in sci_dma_rx_submit()
1436 s->active_rx = s->cookie_rx[0]; in sci_dma_rx_submit()
1451 return -EAGAIN; in sci_dma_rx_submit()
1458 struct dma_chan *chan = s->chan_tx; in sci_dma_tx_work_fn()
1459 struct uart_port *port = &s->port; in sci_dma_tx_work_fn()
1460 struct tty_port *tport = &port->state->port; in sci_dma_tx_work_fn()
1473 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, in sci_dma_tx_work_fn()
1475 buf = s->tx_dma_addr + tail; in sci_dma_tx_work_fn()
1476 if (!s->tx_dma_len) { in sci_dma_tx_work_fn()
1482 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1487 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1491 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1494 desc->callback = sci_dma_tx_complete; in sci_dma_tx_work_fn()
1495 desc->callback_param = s; in sci_dma_tx_work_fn()
1496 s->cookie_tx = dmaengine_submit(desc); in sci_dma_tx_work_fn()
1497 if (dma_submit_error(s->cookie_tx)) { in sci_dma_tx_work_fn()
1499 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1504 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", in sci_dma_tx_work_fn()
1505 __func__, tport->xmit_buf, tail, s->cookie_tx); in sci_dma_tx_work_fn()
1512 s->chan_tx = NULL; in sci_dma_tx_work_fn()
1521 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_timer_fn()
1522 struct uart_port *port = &s->port; in sci_dma_rx_timer_fn()
1529 dev_dbg(port->dev, "DMA Rx timed out\n"); in sci_dma_rx_timer_fn()
1539 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1542 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", in sci_dma_rx_timer_fn()
1543 s->active_rx, active); in sci_dma_rx_timer_fn()
1557 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1560 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); in sci_dma_rx_timer_fn()
1565 dmaengine_terminate_async(s->chan_rx); in sci_dma_rx_timer_fn()
1566 read = sg_dma_len(&s->sg_rx[active]) - state.residue; in sci_dma_rx_timer_fn()
1569 count = sci_dma_rx_push(s, s->rx_buf[active], read); in sci_dma_rx_timer_fn()
1571 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_timer_fn()
1574 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || in sci_dma_rx_timer_fn()
1575 s->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_timer_fn()
1592 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); in sci_request_dma_chan()
1594 dev_dbg(port->dev, "dma_request_chan failed\n"); in sci_request_dma_chan()
1600 cfg.dst_addr = port->mapbase + in sci_request_dma_chan()
1601 (sci_getreg(port, SCxTDR)->offset << port->regshift); in sci_request_dma_chan()
1603 cfg.src_addr = port->mapbase + in sci_request_dma_chan()
1604 (sci_getreg(port, SCxRDR)->offset << port->regshift); in sci_request_dma_chan()
1609 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); in sci_request_dma_chan()
1620 struct tty_port *tport = &port->state->port; in sci_request_dma()
1623 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); in sci_request_dma()
1632 if (!port->dev->of_node) in sci_request_dma()
1635 s->cookie_tx = -EINVAL; in sci_request_dma()
1641 if (!of_property_present(port->dev->of_node, "dmas")) in sci_request_dma()
1645 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); in sci_request_dma()
1647 /* UART circular tx buffer is an aligned page. */ in sci_request_dma()
1648 s->tx_dma_addr = dma_map_single(chan->device->dev, in sci_request_dma()
1649 tport->xmit_buf, in sci_request_dma()
1652 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { in sci_request_dma()
1653 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); in sci_request_dma()
1656 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", in sci_request_dma()
1658 tport->xmit_buf, &s->tx_dma_addr); in sci_request_dma()
1660 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); in sci_request_dma()
1661 s->chan_tx_saved = s->chan_tx = chan; in sci_request_dma()
1666 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); in sci_request_dma()
1672 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); in sci_request_dma()
1673 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, in sci_request_dma()
1676 dev_warn(port->dev, in sci_request_dma()
1683 struct scatterlist *sg = &s->sg_rx[i]; in sci_request_dma()
1686 s->rx_buf[i] = buf; in sci_request_dma()
1688 sg_dma_len(sg) = s->buf_len_rx; in sci_request_dma()
1690 buf += s->buf_len_rx; in sci_request_dma()
1691 dma += s->buf_len_rx; in sci_request_dma()
1694 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in sci_request_dma()
1696 s->chan_rx_saved = s->chan_rx = chan; in sci_request_dma()
1698 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || in sci_request_dma()
1699 s->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_request_dma()
1708 if (s->chan_tx_saved) in sci_free_dma()
1710 if (s->chan_rx_saved) in sci_free_dma()
1723 s->tx_dma_len = 0; in sci_flush_buffer()
1724 if (s->chan_tx) { in sci_flush_buffer()
1725 dmaengine_terminate_async(s->chan_tx); in sci_flush_buffer()
1726 s->cookie_tx = -EINVAL; in sci_flush_buffer()
1735 if (!s->chan_tx) in sci_dma_check_tx_occurred()
1738 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); in sci_dma_check_tx_occurred()
1740 s->tx_occurred = true; in sci_dma_check_tx_occurred()
1764 if (s->chan_rx) { in sci_rx_interrupt()
1769 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || in sci_rx_interrupt()
1770 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1771 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); in sci_rx_interrupt()
1772 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1773 s->ops->set_rtrg(port, 1); in sci_rx_interrupt()
1788 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", in sci_rx_interrupt()
1789 jiffies, s->rx_timeout); in sci_rx_interrupt()
1790 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_rx_interrupt()
1798 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { in sci_rx_interrupt()
1799 if (!s->ops->rtrg_enabled(port)) in sci_rx_interrupt()
1800 s->ops->set_rtrg(port, s->rx_trigger); in sci_rx_interrupt()
1802 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( in sci_rx_interrupt()
1803 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); in sci_rx_interrupt()
1810 s->ops->receive_chars(port); in sci_rx_interrupt()
1822 s->ops->transmit_chars(port); in sci_tx_interrupt()
1832 const struct sci_common_regs *regs = s->params->common_regs; in sci_tx_end_interrupt()
1836 if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI) in sci_tx_end_interrupt()
1840 ctrl = s->ops->read_reg(port, regs->control) & in sci_tx_end_interrupt()
1841 ~(s->params->param_bits->te_clear); in sci_tx_end_interrupt()
1842 s->ops->write_reg(port, regs->control, ctrl); in sci_tx_end_interrupt()
1859 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); in sci_br_interrupt()
1869 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { in sci_er_interrupt()
1883 if (s->type == PORT_SCI) { in sci_er_interrupt()
1887 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); in sci_er_interrupt()
1891 if (!s->chan_rx) in sci_er_interrupt()
1892 s->ops->receive_chars(port); in sci_er_interrupt()
1895 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); in sci_er_interrupt()
1898 if (!s->chan_tx) in sci_er_interrupt()
1913 if (s->params->overrun_reg == SCxSR) in sci_mpxed_interrupt()
1915 else if (sci_getreg(port, s->params->overrun_reg)->size) in sci_mpxed_interrupt()
1916 orer_status = sci_serial_in(port, s->params->overrun_reg); in sci_mpxed_interrupt()
1920 /* Tx Interrupt */ in sci_mpxed_interrupt()
1922 !s->chan_tx) in sci_mpxed_interrupt()
1929 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && in sci_mpxed_interrupt()
1938 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && in sci_mpxed_interrupt()
1943 if (orer_status & s->params->overrun_mask) { in sci_mpxed_interrupt()
1969 .desc = "tx empty",
1984 .desc = "tx end",
1999 struct uart_port *up = &port->port; in sci_request_irq()
2008 if (port->irqs[w] == port->irqs[i]) in sci_request_irq()
2015 irq = up->irq; in sci_request_irq()
2017 irq = port->irqs[i]; in sci_request_irq()
2028 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", in sci_request_irq()
2029 dev_name(up->dev), desc->desc); in sci_request_irq()
2030 if (!port->irqstr[j]) { in sci_request_irq()
2031 ret = -ENOMEM; in sci_request_irq()
2035 ret = request_irq(irq, desc->handler, up->irqflags, in sci_request_irq()
2036 port->irqstr[j], port); in sci_request_irq()
2038 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); in sci_request_irq()
2046 while (--i >= 0) in sci_request_irq()
2047 free_irq(port->irqs[i], port); in sci_request_irq()
2050 while (--j >= 0) in sci_request_irq()
2051 kfree(port->irqstr[j]); in sci_request_irq()
2065 int irq = port->irqs[i]; in sci_free_irq()
2076 if (port->irqs[j] == irq) in sci_free_irq()
2081 free_irq(port->irqs[i], port); in sci_free_irq()
2082 kfree(port->irqstr[i]); in sci_free_irq()
2099 if (!s->tx_occurred) in sci_tx_empty()
2109 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { in sci_set_rts()
2122 } else if (sci_getreg(port, SCSPTR)->size) { in sci_set_rts()
2138 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { in sci_get_cts()
2141 } else if (sci_getreg(port, SCSPTR)->size) { in sci_get_cts()
2153 * handled via the ->init_pins() op, which is a bit of a one-way street,
2154 * lacking any ability to defer pin control -- this will later be
2172 if (reg->size) in sci_set_mctrl()
2177 mctrl_gpio_set(s->gpios, mctrl); in sci_set_mctrl()
2179 if (!s->has_rtscts) in sci_set_mctrl()
2184 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2190 } else if (s->autorts) { in sci_set_mctrl()
2191 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { in sci_set_mctrl()
2198 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2210 struct mctrl_gpios *gpios = s->gpios; in sci_get_mctrl()
2219 if (s->autorts) { in sci_get_mctrl()
2235 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); in sci_enable_ms()
2244 if (!sci_getreg(port, SCSPTR)->size) { in sci_break_ctl()
2256 if (break_state == -1) { in sci_break_ctl()
2276 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); in sci_shutdown_complete()
2284 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_startup()
2286 s->tx_occurred = false; in sci_startup()
2304 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_shutdown()
2306 s->autorts = false; in sci_shutdown()
2307 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios); in sci_shutdown()
2310 s->port.ops->stop_rx(port); in sci_shutdown()
2311 s->port.ops->stop_tx(port); in sci_shutdown()
2312 s->ops->shutdown_complete(port); in sci_shutdown()
2316 if (s->chan_rx_saved) { in sci_shutdown()
2317 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, in sci_shutdown()
2318 port->line); in sci_shutdown()
2319 hrtimer_cancel(&s->rx_timer); in sci_shutdown()
2323 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) in sci_shutdown()
2324 timer_delete_sync(&s->rx_fifo_timer); in sci_shutdown()
2333 unsigned long freq = s->clk_rates[SCI_SCK]; in sci_sck_calc()
2337 if (s->type != PORT_HSCIF) in sci_sck_calc()
2341 err = DIV_ROUND_CLOSEST(freq, sr) - bps; in sci_sck_calc()
2346 *srr = sr - 1; in sci_sck_calc()
2352 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, in sci_sck_calc()
2364 if (s->type != PORT_HSCIF) in sci_brg_calc()
2371 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; in sci_brg_calc()
2377 *srr = sr - 1; in sci_brg_calc()
2383 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, in sci_brg_calc()
2393 unsigned long freq = s->clk_rates[SCI_FCK]; in sci_scbrr_calc()
2397 if (s->type != PORT_HSCIF) in sci_scbrr_calc()
2411 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - in sci_scbrr_calc()
2412 * (|D - 0.5| / N * (1 + F))| in sci_scbrr_calc()
2424 * err = freq / (br * prediv) - bps in sci_scbrr_calc()
2436 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
2441 *brr = br - 1; in sci_scbrr_calc()
2442 *srr = sr - 1; in sci_scbrr_calc()
2451 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, in sci_scbrr_calc()
2462 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ in sci_reset()
2465 if (reg->size) in sci_reset()
2468 s->ops->clear_SCxSR(port, in sci_reset()
2471 if (sci_getreg(port, SCLSR)->size) { in sci_reset()
2477 if (s->rx_trigger > 1) { in sci_reset()
2478 if (s->rx_fifo_timeout) { in sci_reset()
2479 s->ops->set_rtrg(port, 1); in sci_reset()
2480 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); in sci_reset()
2482 if (s->type == PORT_SCIFA || in sci_reset()
2483 s->type == PORT_SCIFB) in sci_reset()
2484 s->ops->set_rtrg(port, 1); in sci_reset()
2486 s->ops->set_rtrg(port, s->rx_trigger); in sci_reset()
2501 int best_clk = -1; in sci_set_termios()
2504 if ((termios->c_cflag & CSIZE) == CS7) { in sci_set_termios()
2507 termios->c_cflag &= ~CSIZE; in sci_set_termios()
2508 termios->c_cflag |= CS8; in sci_set_termios()
2510 if (termios->c_cflag & PARENB) in sci_set_termios()
2512 if (termios->c_cflag & PARODD) in sci_set_termios()
2514 if (termios->c_cflag & CSTOPB) in sci_set_termios()
2518 * earlyprintk comes here early on with port->uartclk set to zero. in sci_set_termios()
2521 * the baud rate is not programmed during earlyprintk - it is assumed in sci_set_termios()
2525 if (!port->uartclk) { in sci_set_termios()
2531 max_freq = max(max_freq, s->clk_rates[i]); in sci_set_termios()
2543 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA && in sci_set_termios()
2544 s->type != PORT_SCIFB) { in sci_set_termios()
2558 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2559 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, in sci_set_termios()
2574 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2575 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, in sci_set_termios()
2602 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", in sci_set_termios()
2603 s->clks[best_clk], baud, min_err); in sci_set_termios()
2611 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { in sci_set_termios()
2620 uart_update_timeout(port, termios->c_cflag, baud); in sci_set_termios()
2623 bits = tty_get_frame_size(termios->c_cflag); in sci_set_termios()
2625 if (sci_getreg(port, SEMR)->size) in sci_set_termios()
2629 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) in sci_set_termios()
2641 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2644 if (sci_getreg(port, HSSRR)->size) { in sci_set_termios()
2649 int last_stop = bits * 2 - 1; in sci_set_termios()
2659 int shift = clamp(deviation / 2, -8, 7); in sci_set_termios()
2669 udelay((1000000 + (baud - 1)) / baud); in sci_set_termios()
2672 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); in sci_set_termios()
2675 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2679 sci_init_pins(port, termios->c_cflag); in sci_set_termios()
2681 port->status &= ~UPSTAT_AUTOCTS; in sci_set_termios()
2682 s->autorts = false; in sci_set_termios()
2684 if (reg->size) { in sci_set_termios()
2687 if ((port->flags & UPF_HARD_FLOW) && in sci_set_termios()
2688 (termios->c_cflag & CRTSCTS)) { in sci_set_termios()
2690 port->status |= UPSTAT_AUTOCTS; in sci_set_termios()
2692 s->autorts = true; in sci_set_termios()
2704 if (port->flags & UPF_HARD_FLOW) { in sci_set_termios()
2706 sci_set_mctrl(port, port->mctrl); in sci_set_termios()
2714 if (s->type != PORT_SCI) in sci_set_termios()
2716 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); in sci_set_termios()
2717 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2719 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) { in sci_set_termios()
2730 s->rx_frame = (10000 * bits) / (baud / 100); in sci_set_termios()
2732 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; in sci_set_termios()
2735 if ((termios->c_cflag & CREAD) != 0) in sci_set_termios()
2742 if (UART_ENABLE_MS(port, termios->c_cflag)) in sci_set_termios()
2766 switch (s->type) { in sci_type()
2791 if (port->membase) in sci_remap_port()
2794 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_remap_port()
2795 port->membase = ioremap(port->mapbase, sport->reg_size); in sci_remap_port()
2796 if (unlikely(!port->membase)) { in sci_remap_port()
2797 dev_err(port->dev, "can't remap port#%d\n", port->line); in sci_remap_port()
2798 return -ENXIO; in sci_remap_port()
2806 port->membase = (void __iomem *)(uintptr_t)port->mapbase; in sci_remap_port()
2816 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_release_port()
2817 iounmap(port->membase); in sci_release_port()
2818 port->membase = NULL; in sci_release_port()
2821 release_mem_region(port->mapbase, sport->reg_size); in sci_release_port()
2831 res = request_mem_region(port->mapbase, sport->reg_size, in sci_request_port()
2832 dev_name(port->dev)); in sci_request_port()
2834 dev_err(port->dev, "request_mem_region failed."); in sci_request_port()
2835 return -EBUSY; in sci_request_port()
2852 port->type = SCI_PUBLIC_PORT_ID(sport->type); in sci_config_port()
2860 if (ser->baud_base < 2400) in sci_verify_port()
2862 return -EINVAL; in sci_verify_port()
2872 s->params->param_bits->rxtx_enable | in sci_prepare_console_write()
2873 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | in sci_prepare_console_write()
2875 s->hscif_tot; in sci_prepare_console_write()
2882 struct sci_suspend_regs *regs = s->suspend_regs; in sci_console_save()
2884 if (sci_getreg(port, SCDL)->size) in sci_console_save()
2885 regs->scdl = sci_serial_in(port, SCDL); in sci_console_save()
2886 if (sci_getreg(port, SCCKS)->size) in sci_console_save()
2887 regs->sccks = sci_serial_in(port, SCCKS); in sci_console_save()
2888 if (sci_getreg(port, SCSMR)->size) in sci_console_save()
2889 regs->scsmr = sci_serial_in(port, SCSMR); in sci_console_save()
2890 if (sci_getreg(port, SCSCR)->size) in sci_console_save()
2891 regs->scscr = sci_serial_in(port, SCSCR); in sci_console_save()
2892 if (sci_getreg(port, SCFCR)->size) in sci_console_save()
2893 regs->scfcr = sci_serial_in(port, SCFCR); in sci_console_save()
2894 if (sci_getreg(port, SCSPTR)->size) in sci_console_save()
2895 regs->scsptr = sci_serial_in(port, SCSPTR); in sci_console_save()
2896 if (sci_getreg(port, SCBRR)->size) in sci_console_save()
2897 regs->scbrr = sci_serial_in(port, SCBRR); in sci_console_save()
2898 if (sci_getreg(port, HSSRR)->size) in sci_console_save()
2899 regs->hssrr = sci_serial_in(port, HSSRR); in sci_console_save()
2900 if (sci_getreg(port, SCPCR)->size) in sci_console_save()
2901 regs->scpcr = sci_serial_in(port, SCPCR); in sci_console_save()
2902 if (sci_getreg(port, SCPDR)->size) in sci_console_save()
2903 regs->scpdr = sci_serial_in(port, SCPDR); in sci_console_save()
2904 if (sci_getreg(port, SEMR)->size) in sci_console_save()
2905 regs->semr = sci_serial_in(port, SEMR); in sci_console_save()
2911 struct sci_suspend_regs *regs = s->suspend_regs; in sci_console_restore()
2913 if (sci_getreg(port, SCDL)->size) in sci_console_restore()
2914 sci_serial_out(port, SCDL, regs->scdl); in sci_console_restore()
2915 if (sci_getreg(port, SCCKS)->size) in sci_console_restore()
2916 sci_serial_out(port, SCCKS, regs->sccks); in sci_console_restore()
2917 if (sci_getreg(port, SCSMR)->size) in sci_console_restore()
2918 sci_serial_out(port, SCSMR, regs->scsmr); in sci_console_restore()
2919 if (sci_getreg(port, SCSCR)->size) in sci_console_restore()
2920 sci_serial_out(port, SCSCR, regs->scscr); in sci_console_restore()
2921 if (sci_getreg(port, SCFCR)->size) in sci_console_restore()
2922 sci_serial_out(port, SCFCR, regs->scfcr); in sci_console_restore()
2923 if (sci_getreg(port, SCSPTR)->size) in sci_console_restore()
2924 sci_serial_out(port, SCSPTR, regs->scsptr); in sci_console_restore()
2925 if (sci_getreg(port, SCBRR)->size) in sci_console_restore()
2926 sci_serial_out(port, SCBRR, regs->scbrr); in sci_console_restore()
2927 if (sci_getreg(port, HSSRR)->size) in sci_console_restore()
2928 sci_serial_out(port, HSSRR, regs->hssrr); in sci_console_restore()
2929 if (sci_getreg(port, SCPCR)->size) in sci_console_restore()
2930 sci_serial_out(port, SCPCR, regs->scpcr); in sci_console_restore()
2931 if (sci_getreg(port, SCPDR)->size) in sci_console_restore()
2932 sci_serial_out(port, SCPDR, regs->scpdr); in sci_console_restore()
2933 if (sci_getreg(port, SEMR)->size) in sci_console_restore()
2934 sci_serial_out(port, SEMR, regs->semr); in sci_console_restore()
2992 if (sci_port->type == PORT_HSCIF) { in sci_init_clocks()
2994 } else if (sci_port->type == SCI_PORT_RSCI) { in sci_init_clocks()
3006 if (!clk && sci_port->type == SCI_PORT_RSCI && in sci_init_clocks()
3008 return dev_err_probe(dev, -ENODEV, in sci_init_clocks()
3031 sci_port->clks[i] = clk; in sci_init_clocks()
3041 sci_port->ops = &sci_port_ops; in sci_probe_regmap()
3042 sci_port->port.ops = &sci_uart_ops; in sci_probe_regmap()
3044 if (cfg->regtype != SCIx_PROBE_REGTYPE) in sci_probe_regmap()
3045 return &sci_port_params[cfg->regtype]; in sci_probe_regmap()
3047 switch (cfg->type) { in sci_probe_regmap()
3062 * The SH-4 is a bit of a misnomer here, although that's in sci_probe_regmap()
3084 struct uart_port *port = &sci_port->port; in sci_init_single()
3089 sci_port->cfg = p; in sci_init_single()
3091 sci_port->type = p->type; in sci_init_single()
3092 sci_port->regtype = p->regtype; in sci_init_single()
3094 port->iotype = UPIO_MEM; in sci_init_single()
3095 port->line = index; in sci_init_single()
3096 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); in sci_init_single()
3100 return -ENOMEM; in sci_init_single()
3102 port->mapbase = res->start; in sci_init_single()
3103 sci_port->reg_size = resource_size(res); in sci_init_single()
3105 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { in sci_init_single()
3107 sci_port->irqs[i] = platform_get_irq_optional(dev, i); in sci_init_single()
3109 sci_port->irqs[i] = platform_get_irq(dev, i); in sci_init_single()
3116 if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI) in sci_init_single()
3117 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); in sci_init_single()
3122 * In the non-muxed case, up to 6 interrupt signals might be generated in sci_init_single()
3126 if (sci_port->irqs[0] < 0) in sci_init_single()
3127 return -ENXIO; in sci_init_single()
3129 if (sci_port->irqs[1] < 0) in sci_init_single()
3130 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) in sci_init_single()
3131 sci_port->irqs[i] = sci_port->irqs[0]; in sci_init_single()
3133 switch (p->type) { in sci_init_single()
3135 sci_port->rx_trigger = 48; in sci_init_single()
3138 sci_port->rx_trigger = 64; in sci_init_single()
3141 sci_port->rx_trigger = 32; in sci_init_single()
3144 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) in sci_init_single()
3146 sci_port->rx_trigger = 1; in sci_init_single()
3148 sci_port->rx_trigger = 8; in sci_init_single()
3151 sci_port->rx_trigger = 15; in sci_init_single()
3154 sci_port->rx_trigger = 1; in sci_init_single()
3158 sci_port->rx_fifo_timeout = 0; in sci_init_single()
3159 sci_port->hscif_tot = 0; in sci_init_single()
3165 sci_port->sampling_rate_mask = p->sampling_rate in sci_init_single()
3166 ? SCI_SR(p->sampling_rate) in sci_init_single()
3167 : sci_port->params->sampling_rate_mask; in sci_init_single()
3170 ret = sci_init_clocks(sci_port, &dev->dev); in sci_init_single()
3175 port->type = SCI_PUBLIC_PORT_ID(p->type); in sci_init_single()
3176 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; in sci_init_single()
3177 port->fifosize = sci_port->params->fifosize; in sci_init_single()
3179 if (p->type == PORT_SCI && !dev->dev.of_node) { in sci_init_single()
3180 if (sci_port->reg_size >= 0x20) in sci_init_single()
3181 port->regshift = 2; in sci_init_single()
3183 port->regshift = 1; in sci_init_single()
3188 * for the multi-IRQ ports, which is where we are primarily in sci_init_single()
3193 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; in sci_init_single()
3194 port->irqflags = 0; in sci_init_single()
3203 to_sci_port(port)->ops->poll_put_char(port, ch); in serial_console_putchar()
3213 struct sci_port *sci_port = &sci_ports[co->index]; in serial_console_write()
3214 struct uart_port *port = &sci_port->port; in serial_console_write()
3215 const struct sci_common_regs *regs = sci_port->params->common_regs; in serial_console_write()
3221 if (port->sysrq) in serial_console_write()
3230 ctrl = sci_port->ops->read_reg(port, regs->control); in serial_console_write()
3231 sci_port->ops->prepare_console_write(port, ctrl); in serial_console_write()
3237 bits = sci_port->params->param_bits->poll_sent_bits; in serial_console_write()
3239 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits) in serial_console_write()
3243 sci_port->ops->write_reg(port, regs->control, ctrl); in serial_console_write()
3262 if (co->index < 0 || co->index >= SCI_NPORTS) in serial_console_setup()
3263 return -ENODEV; in serial_console_setup()
3265 sci_port = &sci_ports[co->index]; in serial_console_setup()
3266 port = &sci_port->port; in serial_console_setup()
3271 if (!port->ops) in serial_console_setup()
3272 return -ENODEV; in serial_console_setup()
3290 .index = -1,
3315 .index = -1,
3320 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); in sci_probe_earlyprintk()
3321 struct sci_port *sp = &sci_ports[pdev->id]; in sci_probe_earlyprintk()
3324 return -EEXIST; in sci_probe_earlyprintk()
3326 early_serial_console.index = pdev->id; in sci_probe_earlyprintk()
3328 sp->params = sci_probe_regmap(cfg, sp); in sci_probe_earlyprintk()
3329 if (!sp->params) in sci_probe_earlyprintk()
3330 return -ENODEV; in sci_probe_earlyprintk()
3332 sci_init_single(pdev, sp, pdev->id, cfg, true); in sci_probe_earlyprintk()
3347 return -EINVAL; in sci_probe_earlyprintk()
3370 unsigned int type = s->type; /* uart_remove_... clears it */ in sci_remove()
3372 sci_ports_in_use &= ~BIT(s->port.line); in sci_remove()
3373 uart_remove_one_port(&sci_uart_driver, &s->port); in sci_remove()
3375 if (s->port.fifosize > 1) in sci_remove()
3376 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_remove()
3379 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_remove()
3455 /* SoC-specific types */
3457 .compatible = "renesas,scif-r7s72100",
3461 .compatible = "renesas,scif-r7s9210",
3465 .compatible = "renesas,scif-r9a07g044",
3469 .compatible = "renesas,scif-r9a09g057",
3474 .compatible = "renesas,r9a09g077-rsci",
3478 /* Family-specific types */
3480 .compatible = "renesas,rcar-gen1-scif",
3483 .compatible = "renesas,rcar-gen2-scif",
3486 .compatible = "renesas,rcar-gen3-scif",
3489 .compatible = "renesas,rcar-gen4-scif",
3492 .compatible = "renesas,rcar-gen5-scif",
3525 struct device_node *np = pdev->dev.of_node; in sci_parse_dt()
3533 return ERR_PTR(-EINVAL); in sci_parse_dt()
3535 data = of_device_get_match_data(&pdev->dev); in sci_parse_dt()
3537 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in sci_parse_dt()
3539 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), in sci_parse_dt()
3544 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); in sci_parse_dt()
3548 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); in sci_parse_dt()
3550 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", in sci_parse_dt()
3555 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); in sci_parse_dt()
3557 return ERR_PTR(-ENOMEM); in sci_parse_dt()
3564 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); in sci_parse_dt()
3565 return ERR_PTR(-EINVAL); in sci_parse_dt()
3568 dev_err(&pdev->dev, "serial%d out of range\n", id); in sci_parse_dt()
3569 return ERR_PTR(-EINVAL); in sci_parse_dt()
3573 sp->rstc = rstc; in sci_parse_dt()
3576 p->type = data->type; in sci_parse_dt()
3577 p->regtype = data->regtype; in sci_parse_dt()
3579 sp->ops = data->ops; in sci_parse_dt()
3580 sp->port.ops = data->uart_ops; in sci_parse_dt()
3581 sp->params = data->params; in sci_parse_dt()
3583 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); in sci_parse_dt()
3598 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", in sci_probe_single()
3600 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); in sci_probe_single()
3601 return -EINVAL; in sci_probe_single()
3605 return -EBUSY; in sci_probe_single()
3621 sciport->port.dev = &dev->dev; in sci_probe_single()
3622 ret = devm_pm_runtime_enable(&dev->dev); in sci_probe_single()
3626 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); in sci_probe_single()
3627 if (IS_ERR(sciport->gpios)) in sci_probe_single()
3628 return PTR_ERR(sciport->gpios); in sci_probe_single()
3630 if (sciport->has_rtscts) { in sci_probe_single()
3631 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || in sci_probe_single()
3632 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { in sci_probe_single()
3633 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); in sci_probe_single()
3634 return -EINVAL; in sci_probe_single()
3636 sciport->port.flags |= UPF_HARD_FLOW; in sci_probe_single()
3639 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { in sci_probe_single()
3642 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and in sci_probe_single()
3643 * - it now maps to an alias other than zero and in sci_probe_single()
3644 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is in sci_probe_single()
3654 pm_runtime_get_noresume(&dev->dev); in sci_probe_single()
3663 return uart_add_one_port(&sci_uart_driver, &sciport->port); in sci_probe_single()
3684 if (dev->dev.of_node) { in sci_probe()
3690 p = dev->dev.platform_data; in sci_probe()
3692 dev_err(&dev->dev, "no platform data supplied\n"); in sci_probe()
3693 return -EINVAL; in sci_probe()
3696 dev_id = dev->id; in sci_probe()
3698 sp->params = sci_probe_regmap(p, sp); in sci_probe()
3699 if (!sp->params) in sci_probe()
3700 return -ENODEV; in sci_probe()
3703 sp->suspend_regs = devm_kzalloc(&dev->dev, in sci_probe()
3704 sp->ops->suspend_regs_size(), in sci_probe()
3706 if (!sp->suspend_regs) in sci_probe()
3707 return -ENOMEM; in sci_probe()
3711 * - the probed port alias is zero (as the one used by earlycon), and in sci_probe()
3712 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in in sci_probe()
3723 return -ENODEV; in sci_probe()
3725 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) in sci_probe()
3726 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); in sci_probe()
3734 if (sp->port.fifosize > 1) { in sci_probe()
3735 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_probe()
3739 if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB || in sci_probe()
3740 sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) { in sci_probe()
3741 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_probe()
3743 if (sp->port.fifosize > 1) { in sci_probe()
3744 device_remove_file(&dev->dev, in sci_probe()
3764 uart_suspend_port(&sci_uart_driver, &sport->port); in sci_suspend()
3766 if (!console_suspend_enabled && uart_console(&sport->port)) { in sci_suspend()
3767 if (sport->ops->console_save) in sci_suspend()
3768 sport->ops->console_save(&sport->port); in sci_suspend()
3771 return reset_control_assert(sport->rstc); in sci_suspend()
3782 if (!console_suspend_enabled && uart_console(&sport->port)) { in sci_resume()
3783 if (sport->ops->console_restore) in sci_resume()
3784 sport->ops->console_restore(&sport->port); in sci_resume()
3786 int ret = reset_control_deassert(sport->rstc); in sci_resume()
3792 uart_resume_port(&sci_uart_driver, &sport->port); in sci_resume()
3804 .name = "sh-sci",
3853 if (!device->port.membase) in scix_early_console_setup()
3854 return -ENODEV; in scix_early_console_setup()
3856 device->port.type = SCI_PUBLIC_PORT_ID(data->type); in scix_early_console_setup()
3858 sci_ports[0].port = device->port; in scix_early_console_setup()
3859 sci_ports[0].type = data->type; in scix_early_console_setup()
3860 sci_ports[0].regtype = data->regtype; in scix_early_console_setup()
3862 port_cfg.type = data->type; in scix_early_console_setup()
3863 port_cfg.regtype = data->regtype; in scix_early_console_setup()
3866 sci_ports[0].params = data->params; in scix_early_console_setup()
3867 sci_ports[0].ops = data->ops; in scix_early_console_setup()
3868 sci_ports[0].port.ops = data->uart_ops; in scix_early_console_setup()
3870 regs = sci_ports[0].params->common_regs; in scix_early_console_setup()
3872 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control); in scix_early_console_setup()
3873 sci_ports[0].ops->write_reg(&sci_ports[0].port, in scix_early_console_setup()
3874 regs->control, in scix_early_console_setup()
3875 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr); in scix_early_console_setup()
3877 device->con->write = serial_console_write; in scix_early_console_setup()
3878 device->con->exit = early_console_exit; in scix_early_console_setup()
3922 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3923 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3924 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3934 MODULE_ALIAS("platform:sh-sci");