Lines Matching refs:tup
151 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
152 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
153 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
156 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, in tegra_uart_read() argument
159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
162 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, in tegra_uart_write() argument
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
175 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_get_mctrl() local
186 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
191 static void set_rts(struct tegra_uart_port *tup, bool active) in set_rts() argument
195 mcr = tup->mcr_shadow; in set_rts()
200 if (mcr != tup->mcr_shadow) { in set_rts()
201 tegra_uart_write(tup, mcr, UART_MCR); in set_rts()
202 tup->mcr_shadow = mcr; in set_rts()
206 static void set_dtr(struct tegra_uart_port *tup, bool active) in set_dtr() argument
210 mcr = tup->mcr_shadow; in set_dtr()
215 if (mcr != tup->mcr_shadow) { in set_dtr()
216 tegra_uart_write(tup, mcr, UART_MCR); in set_dtr()
217 tup->mcr_shadow = mcr; in set_dtr()
221 static void set_loopbk(struct tegra_uart_port *tup, bool active) in set_loopbk() argument
223 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
230 if (mcr != tup->mcr_shadow) { in set_loopbk()
231 tegra_uart_write(tup, mcr, UART_MCR); in set_loopbk()
232 tup->mcr_shadow = mcr; in set_loopbk()
238 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_mctrl() local
241 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
242 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
245 set_dtr(tup, enable); in tegra_uart_set_mctrl()
248 set_loopbk(tup, enable); in tegra_uart_set_mctrl()
253 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_break_ctl() local
256 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
261 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_break_ctl()
262 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
274 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, in tegra_uart_wait_cycle_time() argument
277 if (tup->current_baud) in tegra_uart_wait_cycle_time()
278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
282 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, in tegra_uart_wait_sym_time() argument
285 if (tup->current_baud) in tegra_uart_wait_sym_time()
286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
287 tup->current_baud)); in tegra_uart_wait_sym_time()
290 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup) in tegra_uart_wait_fifo_mode_enabled() argument
296 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_wait_fifo_mode_enabled()
305 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) in tegra_uart_fifo_reset() argument
307 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
310 if (tup->rts_active) in tegra_uart_fifo_reset()
311 set_rts(tup, false); in tegra_uart_fifo_reset()
313 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
315 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
318 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
321 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
323 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
324 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
325 tegra_uart_wait_fifo_mode_enabled(tup); in tegra_uart_fifo_reset()
329 tegra_uart_read(tup, UART_SCR); in tegra_uart_fifo_reset()
336 tegra_uart_wait_cycle_time(tup, 32); in tegra_uart_fifo_reset()
339 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fifo_reset()
345 if (tup->rts_active) in tegra_uart_fifo_reset()
346 set_rts(tup, true); in tegra_uart_fifo_reset()
349 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup, in tegra_get_tolerance_rate() argument
354 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
355 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
356 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
358 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
364 static int tegra_check_rate_in_range(struct tegra_uart_port *tup) in tegra_check_rate_in_range() argument
368 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
369 / tup->required_rate; in tegra_check_rate_in_range()
370 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
371 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
372 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
380 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) in tegra_set_baudrate() argument
388 if (tup->current_baud == baud) in tegra_set_baudrate()
391 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
393 tup->required_rate = rate; in tegra_set_baudrate()
395 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
396 rate = tegra_get_tolerance_rate(tup, baud, rate); in tegra_set_baudrate()
398 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
400 dev_err(tup->uport.dev, in tegra_set_baudrate()
404 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
406 ret = tegra_check_rate_in_range(tup); in tegra_set_baudrate()
410 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
414 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_set_baudrate()
415 lcr = tup->lcr_shadow; in tegra_set_baudrate()
417 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
419 tegra_uart_write(tup, divisor & 0xFF, UART_TX); in tegra_set_baudrate()
420 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); in tegra_set_baudrate()
423 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
426 tegra_uart_read(tup, UART_SCR); in tegra_set_baudrate()
427 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_set_baudrate()
429 tup->current_baud = baud; in tegra_set_baudrate()
432 tegra_uart_wait_sym_time(tup, 2); in tegra_set_baudrate()
436 static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup, in tegra_uart_decode_rx_error() argument
445 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
446 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
450 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
451 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
454 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
455 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
462 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); in tegra_uart_decode_rx_error()
463 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
466 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
467 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
469 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
485 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) in tegra_uart_fill_tx_fifo() argument
491 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
492 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fill_tx_fifo()
496 if (WARN_ON_ONCE(!uart_fifo_get(&tup->uport, &ch))) in tegra_uart_fill_tx_fifo()
498 tegra_uart_write(tup, ch, UART_TX); in tegra_uart_fill_tx_fifo()
502 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, in tegra_uart_start_pio_tx() argument
508 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
509 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
510 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
511 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
516 struct tegra_uart_port *tup = args; in tegra_uart_tx_dma_complete() local
517 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_tx_dma_complete()
522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
523 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
524 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
525 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_uart_tx_dma_complete()
526 uart_xmit_advance(&tup->uport, count); in tegra_uart_tx_dma_complete()
527 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
529 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
530 tegra_uart_start_next_tx(tup); in tegra_uart_tx_dma_complete()
531 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_uart_tx_dma_complete()
534 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, in tegra_uart_start_tx_dma() argument
537 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_start_tx_dma()
541 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
544 tx_phys_addr = tup->tx_dma_buf_phys + tail; in tegra_uart_start_tx_dma()
546 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
547 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
549 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
550 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
552 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
553 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
557 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
558 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
559 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
560 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
561 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
562 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
566 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) in tegra_uart_start_next_tx() argument
568 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_start_next_tx()
573 if (!tup->current_baud) in tegra_uart_start_next_tx()
583 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
584 tegra_uart_start_pio_tx(tup, count); in tegra_uart_start_next_tx()
586 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); in tegra_uart_start_next_tx()
588 tegra_uart_start_tx_dma(tup, count); in tegra_uart_start_next_tx()
594 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_start_tx() local
597 if (!kfifo_is_empty(&tport->xmit_fifo) && !tup->tx_in_progress) in tegra_uart_start_tx()
598 tegra_uart_start_next_tx(tup); in tegra_uart_start_tx()
603 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_tx_empty() local
608 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
609 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_tx_empty()
619 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_tx() local
623 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
626 dmaengine_pause(tup->tx_dma_chan); in tegra_uart_stop_tx()
627 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
628 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
629 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
630 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
631 uart_xmit_advance(&tup->uport, count); in tegra_uart_stop_tx()
632 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
635 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) in tegra_uart_handle_tx_pio() argument
637 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_handle_tx_pio()
639 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
640 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
642 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
643 tegra_uart_start_next_tx(tup); in tegra_uart_handle_tx_pio()
646 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, in tegra_uart_handle_rx_pio() argument
653 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_handle_rx_pio()
657 flag = tegra_uart_decode_rx_error(tup, lsr); in tegra_uart_handle_rx_pio()
661 ch = (unsigned char) tegra_uart_read(tup, UART_RX); in tegra_uart_handle_rx_pio()
662 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
664 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
667 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
674 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, in tegra_uart_copy_rx_to_tty() argument
684 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
686 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
689 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
692 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
695 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
697 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
701 static void do_handle_rx_pio(struct tegra_uart_port *tup) in do_handle_rx_pio() argument
703 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
704 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
706 tegra_uart_handle_rx_pio(tup, port); in do_handle_rx_pio()
713 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, in tegra_uart_rx_buffer_push() argument
716 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
719 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
720 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
723 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_rx_buffer_push()
725 do_handle_rx_pio(tup); in tegra_uart_rx_buffer_push()
730 struct tegra_uart_port *tup = args; in tegra_uart_rx_dma_complete() local
731 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
738 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
741 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
746 if (tup->rts_active) in tegra_uart_rx_dma_complete()
747 set_rts(tup, false); in tegra_uart_rx_dma_complete()
749 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
750 tegra_uart_rx_buffer_push(tup, 0); in tegra_uart_rx_dma_complete()
751 tegra_uart_start_rx_dma(tup); in tegra_uart_rx_dma_complete()
754 if (tup->rts_active) in tegra_uart_rx_dma_complete()
755 set_rts(tup, true); in tegra_uart_rx_dma_complete()
761 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) in tegra_uart_terminate_rx_dma() argument
765 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
766 do_handle_rx_pio(tup); in tegra_uart_terminate_rx_dma()
770 dmaengine_pause(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
771 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
772 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
774 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_terminate_rx_dma()
775 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
778 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) in tegra_uart_handle_rx_dma() argument
781 if (tup->rts_active) in tegra_uart_handle_rx_dma()
782 set_rts(tup, false); in tegra_uart_handle_rx_dma()
784 tegra_uart_terminate_rx_dma(tup); in tegra_uart_handle_rx_dma()
786 if (tup->rts_active) in tegra_uart_handle_rx_dma()
787 set_rts(tup, true); in tegra_uart_handle_rx_dma()
790 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) in tegra_uart_start_rx_dma() argument
794 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
797 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
798 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
800 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
801 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
805 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
806 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
807 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
808 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
809 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
810 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
816 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_handle_modem_signal_change() local
819 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_handle_modem_signal_change()
824 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
826 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
829 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
832 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
837 struct tegra_uart_port *tup = data; in tegra_uart_isr() local
838 struct uart_port *u = &tup->uport; in tegra_uart_isr()
847 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_isr()
849 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
850 tegra_uart_handle_rx_dma(tup); in tegra_uart_isr()
851 if (tup->rx_in_progress) { in tegra_uart_isr()
852 ier = tup->ier_shadow; in tegra_uart_isr()
855 tup->ier_shadow = ier; in tegra_uart_isr()
856 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
859 tegra_uart_start_rx_dma(tup); in tegra_uart_isr()
871 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
872 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
873 tegra_uart_handle_tx_pio(tup); in tegra_uart_isr()
878 if (!tup->use_rx_pio) { in tegra_uart_isr()
879 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
881 ier = tup->ier_shadow; in tegra_uart_isr()
884 tup->ier_shadow = ier; in tegra_uart_isr()
885 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
890 if (!tup->use_rx_pio) { in tegra_uart_isr()
891 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
892 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
893 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
896 do_handle_rx_pio(tup); in tegra_uart_isr()
901 tegra_uart_decode_rx_error(tup, in tegra_uart_isr()
902 tegra_uart_read(tup, UART_LSR)); in tegra_uart_isr()
914 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_rx() local
915 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
918 if (tup->rts_active) in tegra_uart_stop_rx()
919 set_rts(tup, false); in tegra_uart_stop_rx()
921 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
924 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */ in tegra_uart_stop_rx()
926 ier = tup->ier_shadow; in tegra_uart_stop_rx()
929 tup->ier_shadow = ier; in tegra_uart_stop_rx()
930 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_stop_rx()
931 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
933 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
934 tegra_uart_terminate_rx_dma(tup); in tegra_uart_stop_rx()
936 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_stop_rx()
939 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) in tegra_uart_hw_deinit() argument
942 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
943 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
950 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_hw_deinit()
952 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
954 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
955 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
957 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
966 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
967 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
970 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
974 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
978 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_uart_hw_deinit()
980 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); in tegra_uart_hw_deinit()
981 tup->current_baud = 0; in tegra_uart_hw_deinit()
982 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_uart_hw_deinit()
984 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
985 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
987 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
988 tegra_uart_dma_channel_free(tup, true); in tegra_uart_hw_deinit()
989 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
990 tegra_uart_dma_channel_free(tup, false); in tegra_uart_hw_deinit()
992 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
995 static int tegra_uart_hw_init(struct tegra_uart_port *tup) in tegra_uart_hw_init() argument
999 tup->fcr_shadow = 0; in tegra_uart_hw_init()
1000 tup->mcr_shadow = 0; in tegra_uart_hw_init()
1001 tup->lcr_shadow = 0; in tegra_uart_hw_init()
1002 tup->ier_shadow = 0; in tegra_uart_hw_init()
1003 tup->current_baud = 0; in tegra_uart_hw_init()
1005 ret = clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
1007 dev_err(tup->uport.dev, "could not enable clk\n"); in tegra_uart_hw_init()
1012 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1014 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1016 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1017 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1037 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1039 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1040 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1042 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1043 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1045 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1048 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1049 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1052 tegra_uart_read(tup, UART_SCR); in tegra_uart_hw_init()
1054 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1055 ret = tegra_uart_wait_fifo_mode_enabled(tup); in tegra_uart_hw_init()
1057 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1058 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1069 tegra_uart_wait_cycle_time(tup, 3); in tegra_uart_hw_init()
1077 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); in tegra_uart_hw_init()
1079 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1080 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1083 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1084 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1085 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1086 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1088 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1090 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1106 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1112 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1113 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1115 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1119 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, in tegra_uart_dma_channel_free() argument
1123 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1124 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1125 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1126 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1127 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1128 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1129 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1131 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1132 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1133 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1135 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1136 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1137 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1141 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, in tegra_uart_dma_channel_allocate() argument
1150 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1153 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1159 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1163 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1168 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1171 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1173 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1174 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1175 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1176 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1178 dma_buf = tup->uport.state->port.xmit_buf; in tegra_uart_dma_channel_allocate()
1179 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1181 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1182 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1186 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1189 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1190 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1191 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1196 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1198 tegra_uart_dma_channel_free(tup, dma_to_memory); in tegra_uart_dma_channel_allocate()
1207 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_startup() local
1210 if (!tup->use_tx_pio) { in tegra_uart_startup()
1211 ret = tegra_uart_dma_channel_allocate(tup, false); in tegra_uart_startup()
1219 if (!tup->use_rx_pio) { in tegra_uart_startup()
1220 ret = tegra_uart_dma_channel_allocate(tup, true); in tegra_uart_startup()
1228 ret = tegra_uart_hw_init(tup); in tegra_uart_startup()
1235 dev_name(u->dev), tup); in tegra_uart_startup()
1244 clk_disable_unprepare(tup->uart_clk); in tegra_uart_startup()
1246 if (!tup->use_rx_pio) in tegra_uart_startup()
1247 tegra_uart_dma_channel_free(tup, true); in tegra_uart_startup()
1249 if (!tup->use_tx_pio) in tegra_uart_startup()
1250 tegra_uart_dma_channel_free(tup, false); in tegra_uart_startup()
1260 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_flush_buffer() local
1262 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1263 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1264 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1269 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_shutdown() local
1271 tegra_uart_hw_deinit(tup); in tegra_uart_shutdown()
1272 free_irq(u->irq, tup); in tegra_uart_shutdown()
1277 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_enable_ms() local
1279 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1280 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1281 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1289 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_termios() local
1294 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1296 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1303 if (tup->rts_active) in tegra_uart_set_termios()
1304 set_rts(tup, false); in tegra_uart_set_termios()
1307 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1308 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1309 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_set_termios()
1310 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1313 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1341 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_set_termios()
1342 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1343 tup->symb_bit = tty_get_frame_size(termios->c_cflag); in tegra_uart_set_termios()
1350 ret = tegra_set_baudrate(tup, baud); in tegra_uart_set_termios()
1352 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1361 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1362 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1363 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1365 if (tup->rts_active) in tegra_uart_set_termios()
1366 set_rts(tup, true); in tegra_uart_set_termios()
1368 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1369 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1370 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1377 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1380 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1381 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1383 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1386 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1388 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1425 struct tegra_uart_port *tup) in tegra_uart_parse_dt() argument
1440 tup->uport.line = port; in tegra_uart_parse_dt()
1442 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1447 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1452 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1458 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1459 tup->baud_tolerance = in tegra_uart_parse_dt()
1460 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1461 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1462 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1471 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1478 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1485 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1489 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1559 struct tegra_uart_port *tup; in tegra_uart_probe() local
1571 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1572 if (!tup) { in tegra_uart_probe()
1577 ret = tegra_uart_parse_dt(pdev, tup); in tegra_uart_probe()
1581 u = &tup->uport; in tegra_uart_probe()
1586 tup->cdata = cdata; in tegra_uart_probe()
1588 platform_set_drvdata(pdev, tup); in tegra_uart_probe()
1595 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1596 if (IS_ERR(tup->uart_clk)) in tegra_uart_probe()
1597 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock"); in tegra_uart_probe()
1599 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1600 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1602 return PTR_ERR(tup->rst); in tegra_uart_probe()
1621 struct tegra_uart_port *tup = platform_get_drvdata(pdev); in tegra_uart_remove() local
1622 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1630 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_suspend() local
1631 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1638 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_resume() local
1639 struct uart_port *u = &tup->uport; in tegra_uart_resume()