Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
21 #include <linux/soc/qcom/geni-se.h>
27 #include <dt-bindings/interconnect/qcom,icc.h>
175 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode
184 if (!(uport->rs485.flags & SER_RS485_ENABLED)) in qcom_geni_set_rs485_mode()
189 if (uport->rs485.flags & flag) in qcom_geni_set_rs485_mode()
194 writel(rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_set_rs485_mode()
199 struct platform_device *pdev = to_platform_device(uport->dev); in qcom_geni_serial_request_port()
202 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
203 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
204 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
205 port->se.base = uport->membase; in qcom_geni_serial_request_port()
212 uport->type = PORT_MSM; in qcom_geni_serial_config_port()
225 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
243 port->loopback = RX_TX_CTS_RTS_SORTED; in qcom_geni_serial_set_mctrl()
245 if (!(mctrl & TIOCM_RTS) && !uport->suspended) in qcom_geni_serial_set_mctrl()
247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
262 return ERR_PTR(-ENXIO); in get_port_from_line()
270 nr_ports - 1, GFP_KERNEL); in get_port_from_line()
273 nr_ports - 1, GFP_KERNEL); in get_port_from_line()
276 return ERR_PTR(-ENXIO); in get_port_from_line()
280 return ERR_PTR(-ENOMEM); in get_port_from_line()
282 port->uport.iotype = UPIO_MEM; in get_port_from_line()
283 port->uport.ops = &qcom_geni_uart_pops; in get_port_from_line()
284 port->uport.flags = UPF_BOOT_AUTOCONF; in get_port_from_line()
285 port->uport.line = line; in get_port_from_line()
292 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; in qcom_geni_serial_main_active()
297 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; in qcom_geni_serial_secondary_active()
306 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_poll_bitfield()
308 if (private_data->drv) { in qcom_geni_serial_poll_bitfield()
310 if (port->poll_timeout_us) in qcom_geni_serial_poll_bitfield()
311 timeout_us = port->poll_timeout_us; in qcom_geni_serial_poll_bitfield()
320 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bitfield()
324 timeout_us -= 10; in qcom_geni_serial_poll_bitfield()
339 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
341 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
351 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
355 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_tx_done()
363 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); in qcom_geni_serial_abort_rx()
366 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_abort_rx()
367 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); in qcom_geni_serial_abort_rx()
373 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_get_char()
378 if (!private_data->poll_cached_bytes_cnt) { in qcom_geni_serial_get_char()
379 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_get_char()
380 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_get_char()
382 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_get_char()
383 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_get_char()
385 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_get_char()
395 private_data->poll_cached_bytes_cnt = in qcom_geni_serial_get_char()
399 if (private_data->poll_cached_bytes_cnt == 0) in qcom_geni_serial_get_char()
400 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; in qcom_geni_serial_get_char()
402 private_data->poll_cached_bytes = in qcom_geni_serial_get_char()
403 readl(uport->membase + SE_GENI_RX_FIFOn); in qcom_geni_serial_get_char()
406 private_data->poll_cached_bytes_cnt--; in qcom_geni_serial_get_char()
407 ret = private_data->poll_cached_bytes & 0xff; in qcom_geni_serial_get_char()
408 private_data->poll_cached_bytes >>= 8; in qcom_geni_serial_get_char()
421 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_put_char()
423 writel(c, uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_poll_put_char()
432 if (!port->setup) { in qcom_geni_serial_poll_init()
439 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_poll_init()
451 port->tx_queued); in qcom_geni_serial_drain_fifo()
456 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_wr_char()
458 private_data->write_cached_bytes = in qcom_geni_serial_wr_char()
459 (private_data->write_cached_bytes >> 8) | (ch << 24); in qcom_geni_serial_wr_char()
460 private_data->write_cached_bytes_cnt++; in qcom_geni_serial_wr_char()
462 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { in qcom_geni_serial_wr_char()
463 writel(private_data->write_cached_bytes, in qcom_geni_serial_wr_char()
464 uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_wr_char()
465 private_data->write_cached_bytes_cnt = 0; in qcom_geni_serial_wr_char()
473 struct qcom_geni_private_data *private_data = uport->private_data; in __qcom_geni_serial_console_write()
487 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in __qcom_geni_serial_console_write()
488 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_console_write()
492 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; in __qcom_geni_serial_console_write()
503 chars_to_write = min_t(size_t, count - i, avail / 2); in __qcom_geni_serial_console_write()
506 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + in __qcom_geni_serial_console_write()
511 if (private_data->write_cached_bytes_cnt) { in __qcom_geni_serial_console_write()
512 private_data->write_cached_bytes >>= BITS_PER_BYTE * in __qcom_geni_serial_console_write()
513 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); in __qcom_geni_serial_console_write()
514 writel(private_data->write_cached_bytes, in __qcom_geni_serial_console_write()
515 uport->membase + SE_GENI_TX_FIFOn); in __qcom_geni_serial_console_write()
516 private_data->write_cached_bytes_cnt = 0; in __qcom_geni_serial_console_write()
531 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); in qcom_geni_serial_console_write()
533 port = get_port_from_line(co->index, true, NULL); in qcom_geni_serial_console_write()
537 uport = &port->uport; in qcom_geni_serial_console_write()
543 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
544 s_irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_console_write()
545 writel(0, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
546 writel(0, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_console_write()
550 if (!locked || port->tx_remaining == 0) in qcom_geni_serial_console_write()
560 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
561 writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_console_write()
574 tport = &uport->state->port; in handle_rx_console()
577 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); in handle_rx_console()
579 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); in handle_rx_console()
587 uport->icount.rx++; in handle_rx_console()
588 if (port->brk && buf[c] == 0) { in handle_rx_console()
589 port->brk = false; in handle_rx_console()
613 struct tty_port *tport = &uport->state->port; in handle_rx_uart()
616 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); in handle_rx_uart()
618 dev_err_ratelimited(uport->dev, "failed to push data (%d < %u)\n", in handle_rx_uart()
621 uport->icount.rx += ret; in handle_rx_uart()
627 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_tx_empty()
638 if (port->tx_dma_addr) { in qcom_geni_serial_stop_tx_dma()
639 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, in qcom_geni_serial_stop_tx_dma()
640 port->tx_remaining); in qcom_geni_serial_stop_tx_dma()
641 port->tx_dma_addr = 0; in qcom_geni_serial_stop_tx_dma()
642 port->tx_remaining = 0; in qcom_geni_serial_stop_tx_dma()
645 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx_dma()
650 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx_dma()
654 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); in qcom_geni_serial_stop_tx_dma()
655 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_dma()
658 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_dma()
664 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_start_tx_dma()
669 if (port->tx_dma_addr) in qcom_geni_serial_start_tx_dma()
672 if (kfifo_is_empty(&tport->xmit_fifo)) in qcom_geni_serial_start_tx_dma()
675 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, in qcom_geni_serial_start_tx_dma()
682 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, in qcom_geni_serial_start_tx_dma()
683 &port->tx_dma_addr); in qcom_geni_serial_start_tx_dma()
685 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); in qcom_geni_serial_start_tx_dma()
690 port->tx_remaining = xmit_size; in qcom_geni_serial_start_tx_dma()
706 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_start_tx_fifo()
708 writel(c, uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_start_tx_fifo()
712 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx_fifo()
714 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_start_tx_fifo()
715 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx_fifo()
722 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx_fifo()
724 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_stop_tx_fifo()
725 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx_fifo()
732 geni_se_cancel_m_cmd(&port->se); in __qcom_geni_serial_cancel_tx_cmd()
735 geni_se_abort_m_cmd(&port->se); in __qcom_geni_serial_cancel_tx_cmd()
738 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_cancel_tx_cmd()
740 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_cancel_tx_cmd()
752 port->tx_remaining = 0; in qcom_geni_serial_cancel_tx_cmd()
753 port->tx_queued = 0; in qcom_geni_serial_cancel_tx_cmd()
764 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_handle_rx_fifo()
772 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); in qcom_geni_serial_handle_rx_fifo()
786 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
788 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
790 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
792 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
797 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx_fifo()
804 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_stop_rx_fifo()
808 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_stop_rx_fifo()
822 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_start_rx_fifo()
824 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
826 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
828 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
830 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
841 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx_dma()
846 uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_stop_rx_dma()
850 writel(1, uport->membase + SE_DMA_RX_FSM_RST); in qcom_geni_serial_stop_rx_dma()
854 uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_stop_rx_dma()
857 if (port->rx_dma_addr) { in qcom_geni_serial_stop_rx_dma()
858 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, in qcom_geni_serial_stop_rx_dma()
860 port->rx_dma_addr = 0; in qcom_geni_serial_stop_rx_dma()
872 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); in qcom_geni_serial_start_rx_dma()
874 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, in qcom_geni_serial_start_rx_dma()
876 &port->rx_dma_addr); in qcom_geni_serial_start_rx_dma()
878 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); in qcom_geni_serial_start_rx_dma()
892 if (!port->rx_dma_addr) in qcom_geni_serial_handle_rx_dma()
895 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); in qcom_geni_serial_handle_rx_dma()
896 port->rx_dma_addr = 0; in qcom_geni_serial_handle_rx_dma()
898 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); in qcom_geni_serial_handle_rx_dma()
900 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); in qcom_geni_serial_handle_rx_dma()
907 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, in qcom_geni_serial_handle_rx_dma()
909 &port->rx_dma_addr); in qcom_geni_serial_handle_rx_dma()
911 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); in qcom_geni_serial_handle_rx_dma()
918 uport->ops->start_rx(uport); in qcom_geni_serial_start_rx()
923 uport->ops->stop_rx(uport); in qcom_geni_serial_stop_rx()
928 uport->ops->stop_tx(uport); in qcom_geni_serial_stop_tx()
944 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); in qcom_geni_serial_send_chunk_fifo()
946 remaining -= tx_bytes; in qcom_geni_serial_send_chunk_fifo()
947 port->tx_remaining -= tx_bytes; in qcom_geni_serial_send_chunk_fifo()
955 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_handle_tx_fifo()
962 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_handle_tx_fifo()
966 pending = port->tx_remaining; in qcom_geni_serial_handle_tx_fifo()
968 pending = kfifo_len(&tport->xmit_fifo); in qcom_geni_serial_handle_tx_fifo()
977 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); in qcom_geni_serial_handle_tx_fifo()
979 avail = port->tx_fifo_depth; in qcom_geni_serial_handle_tx_fifo()
989 port->tx_remaining = pending; in qcom_geni_serial_handle_tx_fifo()
990 port->tx_queued = 0; in qcom_geni_serial_handle_tx_fifo()
992 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
995 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
999 port->tx_queued += chunk; in qcom_geni_serial_handle_tx_fifo()
1007 uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_handle_tx_fifo()
1010 if (!port->tx_remaining) { in qcom_geni_serial_handle_tx_fifo()
1011 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
1014 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
1017 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in qcom_geni_serial_handle_tx_fifo()
1024 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_handle_tx_dma()
1026 uart_xmit_advance(uport, port->tx_remaining); in qcom_geni_serial_handle_tx_dma()
1027 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); in qcom_geni_serial_handle_tx_dma()
1028 port->tx_dma_addr = 0; in qcom_geni_serial_handle_tx_dma()
1029 port->tx_remaining = 0; in qcom_geni_serial_handle_tx_dma()
1031 if (!kfifo_is_empty(&tport->xmit_fifo)) in qcom_geni_serial_handle_tx_dma()
1034 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in qcom_geni_serial_handle_tx_dma()
1049 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_isr()
1052 if (uport->suspended) in qcom_geni_serial_isr()
1057 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_isr()
1058 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_isr()
1059 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); in qcom_geni_serial_isr()
1060 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); in qcom_geni_serial_isr()
1061 geni_status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_isr()
1062 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); in qcom_geni_serial_isr()
1063 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_isr()
1064 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_isr()
1065 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_isr()
1066 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); in qcom_geni_serial_isr()
1067 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_isr()
1073 uport->icount.overrun++; in qcom_geni_serial_isr()
1079 uport->icount.parity++; in qcom_geni_serial_isr()
1082 uport->icount.brk++; in qcom_geni_serial_isr()
1083 port->brk = true; in qcom_geni_serial_isr()
1097 uport->icount.parity++; in qcom_geni_serial_isr()
1102 uport->icount.brk++; in qcom_geni_serial_isr()
1127 u32 old_rx_fifo_depth = port->rx_fifo_depth; in setup_fifos()
1129 uport = &port->uport; in setup_fifos()
1130 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); in setup_fifos()
1131 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); in setup_fifos()
1132 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); in setup_fifos()
1133 uport->fifosize = in setup_fifos()
1134 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; in setup_fifos()
1136 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { in setup_fifos()
1142 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, in setup_fifos()
1143 port->rx_fifo_depth * sizeof(u32), in setup_fifos()
1145 if (!port->rx_buf) in setup_fifos()
1146 return -ENOMEM; in setup_fifos()
1155 disable_irq(uport->irq); in qcom_geni_serial_shutdown()
1178 proto = geni_se_read_proto(&port->se); in qcom_geni_serial_port_setup()
1180 ret = geni_load_se_firmware(&port->se, GENI_SE_UART); in qcom_geni_serial_port_setup()
1182 dev_err(uport->dev, "UART firmware load failed ret: %d\n", ret); in qcom_geni_serial_port_setup()
1186 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); in qcom_geni_serial_port_setup()
1187 return -ENXIO; in qcom_geni_serial_port_setup()
1196 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); in qcom_geni_serial_port_setup()
1198 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
1199 if (port->rx_tx_swap) { in qcom_geni_serial_port_setup()
1203 if (port->cts_rts_swap) { in qcom_geni_serial_port_setup()
1207 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ in qcom_geni_serial_port_setup()
1208 if (port->rx_tx_swap || port->cts_rts_swap) in qcom_geni_serial_port_setup()
1209 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
1217 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, in qcom_geni_serial_port_setup()
1219 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); in qcom_geni_serial_port_setup()
1220 geni_se_select_mode(&port->se, port->dev_data->mode); in qcom_geni_serial_port_setup()
1221 port->setup = true; in qcom_geni_serial_port_setup()
1231 if (!port->setup) { in qcom_geni_serial_startup()
1241 enable_irq(uport->irq); in qcom_geni_serial_startup()
1258 ver = geni_se_get_qup_hw_version(&port->se); in geni_serial_set_rate()
1262 ret = geni_se_clk_freq_match(&port->se, baud * sampling_rate, &clk_idx, &clk_rate, false); in geni_serial_set_rate()
1264 dev_err(port->se.dev, "Failed to find src clk for baud rate: %d ret: %d\n", in geni_serial_set_rate()
1272 dev_err(port->se.dev, "Calculated clock divider %u exceeds maximum\n", clk_div); in geni_serial_set_rate()
1273 return -EINVAL; in geni_serial_set_rate()
1276 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n, clk_idx = %u\n", in geni_serial_set_rate()
1279 uport->uartclk = clk_rate; in geni_serial_set_rate()
1280 port->clk_rate = clk_rate; in geni_serial_set_rate()
1281 dev_pm_opp_set_rate(uport->dev, clk_rate); in geni_serial_set_rate()
1291 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; in geni_serial_set_rate()
1292 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); in geni_serial_set_rate()
1293 geni_icc_set_bw(&port->se); in geni_serial_set_rate()
1295 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); in geni_serial_set_rate()
1296 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); in geni_serial_set_rate()
1298 writel(clk_idx & CLK_SEL_MSK, uport->membase + SE_GENI_CLK_SEL); in geni_serial_set_rate()
1325 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1326 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1327 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1328 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1329 if (termios->c_cflag & PARENB) { in qcom_geni_serial_set_termios()
1334 if (termios->c_cflag & PARODD) { in qcom_geni_serial_set_termios()
1337 } else if (termios->c_cflag & CMSPAR) { in qcom_geni_serial_set_termios()
1352 bits_per_char = tty_get_char_size(termios->c_cflag); in qcom_geni_serial_set_termios()
1355 if (termios->c_cflag & CSTOPB) in qcom_geni_serial_set_termios()
1361 if (termios->c_cflag & CRTSCTS) in qcom_geni_serial_set_termios()
1367 uart_update_timeout(uport, termios->c_cflag, baud); in qcom_geni_serial_set_termios()
1371 * the FIFO, two-word intermediate transfer register and shift in qcom_geni_serial_set_termios()
1377 timeout += 3 * timeout / port->tx_fifo_depth; in qcom_geni_serial_set_termios()
1378 WRITE_ONCE(port->poll_timeout_us, timeout); in qcom_geni_serial_set_termios()
1382 writel(port->loopback, in qcom_geni_serial_set_termios()
1383 uport->membase + SE_UART_LOOPBACK_CFG); in qcom_geni_serial_set_termios()
1384 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1385 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1386 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1387 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1388 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_set_termios()
1389 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_set_termios()
1390 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_set_termios()
1404 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) in qcom_geni_console_setup()
1405 return -ENXIO; in qcom_geni_console_setup()
1407 port = get_port_from_line(co->index, true, NULL); in qcom_geni_console_setup()
1409 pr_err("Invalid line %d\n", co->index); in qcom_geni_console_setup()
1413 uport = &port->uport; in qcom_geni_console_setup()
1415 if (unlikely(!uport->membase)) in qcom_geni_console_setup()
1416 return -ENXIO; in qcom_geni_console_setup()
1418 if (!port->setup) { in qcom_geni_console_setup()
1433 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_write()
1435 __qcom_geni_serial_console_write(&dev->port, s, n); in qcom_geni_serial_earlycon_write()
1442 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_read()
1443 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_read()
1461 con->read = qcom_geni_serial_earlycon_read; in qcom_geni_serial_enable_early_read()
1473 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_setup()
1478 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ in qcom_geni_serial_earlycon_setup()
1482 if (!uport->membase) in qcom_geni_serial_earlycon_setup()
1483 return -EINVAL; in qcom_geni_serial_earlycon_setup()
1485 uport->private_data = &earlycon_private_data; in qcom_geni_serial_earlycon_setup()
1488 se.base = uport->membase; in qcom_geni_serial_earlycon_setup()
1490 return -ENXIO; in qcom_geni_serial_earlycon_setup()
1506 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); in qcom_geni_serial_earlycon_setup()
1509 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1510 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1511 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1512 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1513 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1514 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1515 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_earlycon_setup()
1517 dev->con->write = qcom_geni_serial_earlycon_write; in qcom_geni_serial_earlycon_setup()
1518 dev->con->setup = NULL; in qcom_geni_serial_earlycon_setup()
1519 qcom_geni_serial_enable_early_read(&se, dev->con); in qcom_geni_serial_earlycon_setup()
1523 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1542 .index = -1,
1576 ret = geni_icc_enable(&port->se); in geni_serial_resources_on()
1580 ret = geni_se_resources_on(&port->se); in geni_serial_resources_on()
1582 geni_icc_disable(&port->se); in geni_serial_resources_on()
1586 if (port->clk_rate) in geni_serial_resources_on()
1587 dev_pm_opp_set_rate(uport->dev, port->clk_rate); in geni_serial_resources_on()
1597 dev_pm_opp_set_rate(uport->dev, 0); in geni_serial_resources_off()
1598 ret = geni_se_resources_off(&port->se); in geni_serial_resources_off()
1602 geni_icc_disable(&port->se); in geni_serial_resources_off()
1611 port->se.clk = devm_clk_get(port->se.dev, "se"); in geni_serial_resource_init()
1612 if (IS_ERR(port->se.clk)) { in geni_serial_resource_init()
1613 ret = PTR_ERR(port->se.clk); in geni_serial_resource_init()
1614 dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); in geni_serial_resource_init()
1618 ret = geni_icc_get(&port->se, NULL); in geni_serial_resource_init()
1622 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; in geni_serial_resource_init()
1623 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in geni_serial_resource_init()
1626 ret = geni_icc_set_bw(&port->se); in geni_serial_resource_init()
1630 ret = devm_pm_opp_set_clkname(port->se.dev, "se"); in geni_serial_resource_init()
1634 /* OPP table is optional */ in geni_serial_resource_init()
1635 ret = devm_pm_opp_of_add_table(port->se.dev); in geni_serial_resource_init()
1636 if (ret && ret != -ENODEV) { in geni_serial_resource_init()
1637 dev_err(port->se.dev, "invalid OPP table in device tree\n"); in geni_serial_resource_init()
1661 * qcom_geni_rs485_config - Configure RS485 settings for the UART port
1729 data = of_device_get_match_data(&pdev->dev); in qcom_geni_serial_probe()
1731 return -EINVAL; in qcom_geni_serial_probe()
1733 if (data->console) { in qcom_geni_serial_probe()
1735 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1738 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1739 if (line == -ENODEV) /* compat with non-standard aliases */ in qcom_geni_serial_probe()
1740 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); in qcom_geni_serial_probe()
1743 port = get_port_from_line(line, data->console, &pdev->dev); in qcom_geni_serial_probe()
1745 dev_err(&pdev->dev, "Invalid line %d\n", line); in qcom_geni_serial_probe()
1749 uport = &port->uport; in qcom_geni_serial_probe()
1751 if (uport->private_data) in qcom_geni_serial_probe()
1752 return -ENODEV; in qcom_geni_serial_probe()
1754 uport->dev = &pdev->dev; in qcom_geni_serial_probe()
1755 port->dev_data = data; in qcom_geni_serial_probe()
1756 port->se.dev = &pdev->dev; in qcom_geni_serial_probe()
1757 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); in qcom_geni_serial_probe()
1765 return -EINVAL; in qcom_geni_serial_probe()
1766 uport->mapbase = res->start; in qcom_geni_serial_probe()
1768 uport->rs485_config = qcom_geni_rs485_config; in qcom_geni_serial_probe()
1769 uport->rs485_supported = qcom_geni_rs485_supported; in qcom_geni_serial_probe()
1770 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1771 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1772 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; in qcom_geni_serial_probe()
1774 if (!data->console) { in qcom_geni_serial_probe()
1775 port->rx_buf = devm_kzalloc(uport->dev, in qcom_geni_serial_probe()
1777 if (!port->rx_buf) in qcom_geni_serial_probe()
1778 return -ENOMEM; in qcom_geni_serial_probe()
1781 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, in qcom_geni_serial_probe()
1783 uart_console(uport) ? "console" : "uart", uport->line); in qcom_geni_serial_probe()
1784 if (!port->name) in qcom_geni_serial_probe()
1785 return -ENOMEM; in qcom_geni_serial_probe()
1790 uport->irq = irq; in qcom_geni_serial_probe()
1791 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); in qcom_geni_serial_probe()
1793 if (!data->console) in qcom_geni_serial_probe()
1794 port->wakeup_irq = platform_get_irq_optional(pdev, 1); in qcom_geni_serial_probe()
1796 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) in qcom_geni_serial_probe()
1797 port->rx_tx_swap = true; in qcom_geni_serial_probe()
1799 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) in qcom_geni_serial_probe()
1800 port->cts_rts_swap = true; in qcom_geni_serial_probe()
1802 port->private_data.drv = drv; in qcom_geni_serial_probe()
1803 uport->private_data = &port->private_data; in qcom_geni_serial_probe()
1806 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); in qcom_geni_serial_probe()
1807 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, in qcom_geni_serial_probe()
1808 IRQF_TRIGGER_HIGH, port->name, uport); in qcom_geni_serial_probe()
1810 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); in qcom_geni_serial_probe()
1822 if (port->wakeup_irq > 0) { in qcom_geni_serial_probe()
1823 device_init_wakeup(&pdev->dev, true); in qcom_geni_serial_probe()
1824 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in qcom_geni_serial_probe()
1825 port->wakeup_irq); in qcom_geni_serial_probe()
1827 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_probe()
1828 ida_free(&port_ida, uport->line); in qcom_geni_serial_probe()
1840 struct uart_port *uport = &port->uport; in qcom_geni_serial_remove()
1841 struct uart_driver *drv = port->private_data.drv; in qcom_geni_serial_remove()
1843 dev_pm_clear_wake_irq(&pdev->dev); in qcom_geni_serial_remove()
1844 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_remove()
1845 ida_free(&port_ida, uport->line); in qcom_geni_serial_remove()
1846 uart_remove_one_port(drv, &port->uport); in qcom_geni_serial_remove()
1852 struct uart_port *uport = &port->uport; in qcom_geni_serial_suspend()
1853 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_suspend()
1860 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); in qcom_geni_serial_suspend()
1861 geni_icc_set_bw(&port->se); in qcom_geni_serial_suspend()
1863 return uart_suspend_port(private_data->drv, uport); in qcom_geni_serial_suspend()
1870 struct uart_port *uport = &port->uport; in qcom_geni_serial_resume()
1871 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_resume()
1873 ret = uart_resume_port(private_data->drv, uport); in qcom_geni_serial_resume()
1875 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); in qcom_geni_serial_resume()
1876 geni_icc_set_bw(&port->se); in qcom_geni_serial_resume()
1897 .compatible = "qcom,geni-debug-uart",
1901 .compatible = "qcom,geni-uart",
1950 MODULE_LICENSE("GPL v2");