Lines Matching +full:cts +full:- +full:rts +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
18 #include <linux/soc/qcom/geni-se.h>
24 #include <dt-bindings/interconnect/qcom,icc.h>
90 /* UART pin swap value */
195 struct platform_device *pdev = to_platform_device(uport->dev); in qcom_geni_serial_request_port()
198 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
199 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
200 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
201 port->se.base = uport->membase; in qcom_geni_serial_request_port()
208 uport->type = PORT_MSM; in qcom_geni_serial_config_port()
221 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
239 port->loopback = RX_TX_CTS_RTS_SORTED; in qcom_geni_serial_set_mctrl()
241 if (!(mctrl & TIOCM_RTS) && !uport->suspended) in qcom_geni_serial_set_mctrl()
243 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
257 return ERR_PTR(-ENXIO); in get_port_from_line()
265 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; in qcom_geni_serial_main_active()
270 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; in qcom_geni_serial_secondary_active()
279 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_poll_bitfield()
281 if (private_data->drv) { in qcom_geni_serial_poll_bitfield()
283 if (port->poll_timeout_us) in qcom_geni_serial_poll_bitfield()
284 timeout_us = port->poll_timeout_us; in qcom_geni_serial_poll_bitfield()
293 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bitfield()
297 timeout_us -= 10; in qcom_geni_serial_poll_bitfield()
312 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
314 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
324 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
328 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_tx_done()
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); in qcom_geni_serial_abort_rx()
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_abort_rx()
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); in qcom_geni_serial_abort_rx()
346 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_get_char()
351 if (!private_data->poll_cached_bytes_cnt) { in qcom_geni_serial_get_char()
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_get_char()
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_get_char()
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_get_char()
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_get_char()
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_get_char()
368 private_data->poll_cached_bytes_cnt = in qcom_geni_serial_get_char()
372 if (private_data->poll_cached_bytes_cnt == 0) in qcom_geni_serial_get_char()
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; in qcom_geni_serial_get_char()
375 private_data->poll_cached_bytes = in qcom_geni_serial_get_char()
376 readl(uport->membase + SE_GENI_RX_FIFOn); in qcom_geni_serial_get_char()
379 private_data->poll_cached_bytes_cnt--; in qcom_geni_serial_get_char()
380 ret = private_data->poll_cached_bytes & 0xff; in qcom_geni_serial_get_char()
381 private_data->poll_cached_bytes >>= 8; in qcom_geni_serial_get_char()
394 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_put_char()
396 writel(c, uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_poll_put_char()
405 if (!port->setup) { in qcom_geni_serial_poll_init()
412 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_poll_init()
424 port->tx_queued); in qcom_geni_serial_drain_fifo()
429 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_wr_char()
431 private_data->write_cached_bytes = in qcom_geni_serial_wr_char()
432 (private_data->write_cached_bytes >> 8) | (ch << 24); in qcom_geni_serial_wr_char()
433 private_data->write_cached_bytes_cnt++; in qcom_geni_serial_wr_char()
435 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { in qcom_geni_serial_wr_char()
436 writel(private_data->write_cached_bytes, in qcom_geni_serial_wr_char()
437 uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_wr_char()
438 private_data->write_cached_bytes_cnt = 0; in qcom_geni_serial_wr_char()
446 struct qcom_geni_private_data *private_data = uport->private_data; in __qcom_geni_serial_console_write()
460 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in __qcom_geni_serial_console_write()
461 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_console_write()
465 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; in __qcom_geni_serial_console_write()
476 chars_to_write = min_t(size_t, count - i, avail / 2); in __qcom_geni_serial_console_write()
479 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + in __qcom_geni_serial_console_write()
484 if (private_data->write_cached_bytes_cnt) { in __qcom_geni_serial_console_write()
485 private_data->write_cached_bytes >>= BITS_PER_BYTE * in __qcom_geni_serial_console_write()
486 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); in __qcom_geni_serial_console_write()
487 writel(private_data->write_cached_bytes, in __qcom_geni_serial_console_write()
488 uport->membase + SE_GENI_TX_FIFOn); in __qcom_geni_serial_console_write()
489 private_data->write_cached_bytes_cnt = 0; in __qcom_geni_serial_console_write()
504 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); in qcom_geni_serial_console_write()
506 port = get_port_from_line(co->index, true); in qcom_geni_serial_console_write()
510 uport = &port->uport; in qcom_geni_serial_console_write()
516 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
517 s_irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_console_write()
518 writel(0, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
519 writel(0, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_console_write()
523 if (!locked || port->tx_remaining == 0) in qcom_geni_serial_console_write()
533 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
534 writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_console_write()
547 tport = &uport->state->port; in handle_rx_console()
550 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); in handle_rx_console()
552 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); in handle_rx_console()
560 uport->icount.rx++; in handle_rx_console()
561 if (port->brk && buf[c] == 0) { in handle_rx_console()
562 port->brk = false; in handle_rx_console()
586 struct tty_port *tport = &uport->state->port; in handle_rx_uart()
589 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); in handle_rx_uart()
591 dev_err_ratelimited(uport->dev, "failed to push data (%d < %u)\n", in handle_rx_uart()
594 uport->icount.rx += ret; in handle_rx_uart()
600 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_tx_empty()
611 if (port->tx_dma_addr) { in qcom_geni_serial_stop_tx_dma()
612 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, in qcom_geni_serial_stop_tx_dma()
613 port->tx_remaining); in qcom_geni_serial_stop_tx_dma()
614 port->tx_dma_addr = 0; in qcom_geni_serial_stop_tx_dma()
615 port->tx_remaining = 0; in qcom_geni_serial_stop_tx_dma()
618 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx_dma()
623 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx_dma()
627 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); in qcom_geni_serial_stop_tx_dma()
628 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_dma()
631 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_dma()
637 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_start_tx_dma()
642 if (port->tx_dma_addr) in qcom_geni_serial_start_tx_dma()
645 if (kfifo_is_empty(&tport->xmit_fifo)) in qcom_geni_serial_start_tx_dma()
648 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, in qcom_geni_serial_start_tx_dma()
653 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, in qcom_geni_serial_start_tx_dma()
654 &port->tx_dma_addr); in qcom_geni_serial_start_tx_dma()
656 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); in qcom_geni_serial_start_tx_dma()
661 port->tx_remaining = xmit_size; in qcom_geni_serial_start_tx_dma()
677 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_start_tx_fifo()
679 writel(c, uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_start_tx_fifo()
683 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx_fifo()
685 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_start_tx_fifo()
686 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx_fifo()
693 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx_fifo()
695 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_stop_tx_fifo()
696 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx_fifo()
703 geni_se_cancel_m_cmd(&port->se); in __qcom_geni_serial_cancel_tx_cmd()
706 geni_se_abort_m_cmd(&port->se); in __qcom_geni_serial_cancel_tx_cmd()
709 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_cancel_tx_cmd()
711 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_cancel_tx_cmd()
723 port->tx_remaining = 0; in qcom_geni_serial_cancel_tx_cmd()
724 port->tx_queued = 0; in qcom_geni_serial_cancel_tx_cmd()
735 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_handle_rx_fifo()
743 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); in qcom_geni_serial_handle_rx_fifo()
757 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
759 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
761 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
763 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
768 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx_fifo()
775 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_stop_rx_fifo()
779 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_stop_rx_fifo()
793 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_start_rx_fifo()
795 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
797 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
799 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
801 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
812 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx_dma()
817 uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_stop_rx_dma()
821 writel(1, uport->membase + SE_DMA_RX_FSM_RST); in qcom_geni_serial_stop_rx_dma()
825 uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_stop_rx_dma()
828 if (port->rx_dma_addr) { in qcom_geni_serial_stop_rx_dma()
829 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, in qcom_geni_serial_stop_rx_dma()
831 port->rx_dma_addr = 0; in qcom_geni_serial_stop_rx_dma()
843 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); in qcom_geni_serial_start_rx_dma()
845 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, in qcom_geni_serial_start_rx_dma()
847 &port->rx_dma_addr); in qcom_geni_serial_start_rx_dma()
849 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); in qcom_geni_serial_start_rx_dma()
863 if (!port->rx_dma_addr) in qcom_geni_serial_handle_rx_dma()
866 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); in qcom_geni_serial_handle_rx_dma()
867 port->rx_dma_addr = 0; in qcom_geni_serial_handle_rx_dma()
869 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); in qcom_geni_serial_handle_rx_dma()
871 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); in qcom_geni_serial_handle_rx_dma()
878 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, in qcom_geni_serial_handle_rx_dma()
880 &port->rx_dma_addr); in qcom_geni_serial_handle_rx_dma()
882 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); in qcom_geni_serial_handle_rx_dma()
889 uport->ops->start_rx(uport); in qcom_geni_serial_start_rx()
894 uport->ops->stop_rx(uport); in qcom_geni_serial_stop_rx()
899 uport->ops->stop_tx(uport); in qcom_geni_serial_stop_tx()
915 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); in qcom_geni_serial_send_chunk_fifo()
917 remaining -= tx_bytes; in qcom_geni_serial_send_chunk_fifo()
918 port->tx_remaining -= tx_bytes; in qcom_geni_serial_send_chunk_fifo()
926 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_handle_tx_fifo()
933 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_handle_tx_fifo()
937 pending = port->tx_remaining; in qcom_geni_serial_handle_tx_fifo()
939 pending = kfifo_len(&tport->xmit_fifo); in qcom_geni_serial_handle_tx_fifo()
948 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); in qcom_geni_serial_handle_tx_fifo()
950 avail = port->tx_fifo_depth; in qcom_geni_serial_handle_tx_fifo()
960 port->tx_remaining = pending; in qcom_geni_serial_handle_tx_fifo()
961 port->tx_queued = 0; in qcom_geni_serial_handle_tx_fifo()
963 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
966 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
970 port->tx_queued += chunk; in qcom_geni_serial_handle_tx_fifo()
978 uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_handle_tx_fifo()
981 if (!port->tx_remaining) { in qcom_geni_serial_handle_tx_fifo()
982 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
985 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
988 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in qcom_geni_serial_handle_tx_fifo()
995 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_handle_tx_dma()
997 uart_xmit_advance(uport, port->tx_remaining); in qcom_geni_serial_handle_tx_dma()
998 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); in qcom_geni_serial_handle_tx_dma()
999 port->tx_dma_addr = 0; in qcom_geni_serial_handle_tx_dma()
1000 port->tx_remaining = 0; in qcom_geni_serial_handle_tx_dma()
1002 if (!kfifo_is_empty(&tport->xmit_fifo)) in qcom_geni_serial_handle_tx_dma()
1005 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in qcom_geni_serial_handle_tx_dma()
1020 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_isr()
1023 if (uport->suspended) in qcom_geni_serial_isr()
1028 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_isr()
1029 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_isr()
1030 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); in qcom_geni_serial_isr()
1031 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); in qcom_geni_serial_isr()
1032 geni_status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_isr()
1033 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); in qcom_geni_serial_isr()
1034 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_isr()
1035 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_isr()
1036 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_isr()
1037 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); in qcom_geni_serial_isr()
1038 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_isr()
1044 uport->icount.overrun++; in qcom_geni_serial_isr()
1050 uport->icount.parity++; in qcom_geni_serial_isr()
1053 uport->icount.brk++; in qcom_geni_serial_isr()
1054 port->brk = true; in qcom_geni_serial_isr()
1066 uport->icount.parity++; in qcom_geni_serial_isr()
1071 uport->icount.brk++; in qcom_geni_serial_isr()
1096 u32 old_rx_fifo_depth = port->rx_fifo_depth; in setup_fifos()
1098 uport = &port->uport; in setup_fifos()
1099 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); in setup_fifos()
1100 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); in setup_fifos()
1101 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); in setup_fifos()
1102 uport->fifosize = in setup_fifos()
1103 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; in setup_fifos()
1105 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { in setup_fifos()
1111 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, in setup_fifos()
1112 port->rx_fifo_depth * sizeof(u32), in setup_fifos()
1114 if (!port->rx_buf) in setup_fifos()
1115 return -ENOMEM; in setup_fifos()
1124 disable_irq(uport->irq); in qcom_geni_serial_shutdown()
1147 proto = geni_se_read_proto(&port->se); in qcom_geni_serial_port_setup()
1149 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); in qcom_geni_serial_port_setup()
1150 return -ENXIO; in qcom_geni_serial_port_setup()
1159 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); in qcom_geni_serial_port_setup()
1161 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
1162 if (port->rx_tx_swap) { in qcom_geni_serial_port_setup()
1166 if (port->cts_rts_swap) { in qcom_geni_serial_port_setup()
1170 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ in qcom_geni_serial_port_setup()
1171 if (port->rx_tx_swap || port->cts_rts_swap) in qcom_geni_serial_port_setup()
1172 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
1180 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, in qcom_geni_serial_port_setup()
1182 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); in qcom_geni_serial_port_setup()
1183 geni_se_select_mode(&port->se, port->dev_data->mode); in qcom_geni_serial_port_setup()
1184 port->setup = true; in qcom_geni_serial_port_setup()
1194 if (!port->setup) { in qcom_geni_serial_startup()
1204 enable_irq(uport->irq); in qcom_geni_serial_startup()
1226 freq = clk_round_rate(clk, mult - offset); in find_clk_rate_in_tol()
1229 if (freq < mult - offset) in find_clk_rate_in_tol()
1233 * Re-calculate div in case rounding skipped rates but we in find_clk_rate_in_tol()
1239 achieved >= desired_clk - abs_tol) { in find_clk_rate_in_tol()
1294 ver = geni_se_get_qup_hw_version(&port->se); in qcom_geni_serial_set_termios()
1298 clk_rate = get_clk_div_rate(port->se.clk, baud, in qcom_geni_serial_set_termios()
1301 dev_err(port->se.dev, in qcom_geni_serial_set_termios()
1307 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", in qcom_geni_serial_set_termios()
1310 uport->uartclk = clk_rate; in qcom_geni_serial_set_termios()
1311 port->clk_rate = clk_rate; in qcom_geni_serial_set_termios()
1312 dev_pm_opp_set_rate(uport->dev, clk_rate); in qcom_geni_serial_set_termios()
1322 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; in qcom_geni_serial_set_termios()
1323 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); in qcom_geni_serial_set_termios()
1324 geni_icc_set_bw(&port->se); in qcom_geni_serial_set_termios()
1327 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1328 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1329 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1330 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1331 if (termios->c_cflag & PARENB) { in qcom_geni_serial_set_termios()
1336 if (termios->c_cflag & PARODD) { in qcom_geni_serial_set_termios()
1339 } else if (termios->c_cflag & CMSPAR) { in qcom_geni_serial_set_termios()
1354 bits_per_char = tty_get_char_size(termios->c_cflag); in qcom_geni_serial_set_termios()
1357 if (termios->c_cflag & CSTOPB) in qcom_geni_serial_set_termios()
1363 if (termios->c_cflag & CRTSCTS) in qcom_geni_serial_set_termios()
1369 uart_update_timeout(uport, termios->c_cflag, baud); in qcom_geni_serial_set_termios()
1373 * the FIFO, two-word intermediate transfer register and shift in qcom_geni_serial_set_termios()
1379 timeout += 3 * timeout / port->tx_fifo_depth; in qcom_geni_serial_set_termios()
1380 WRITE_ONCE(port->poll_timeout_us, timeout); in qcom_geni_serial_set_termios()
1384 writel(port->loopback, in qcom_geni_serial_set_termios()
1385 uport->membase + SE_UART_LOOPBACK_CFG); in qcom_geni_serial_set_termios()
1386 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1387 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1388 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1389 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1390 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_set_termios()
1391 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_set_termios()
1392 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_set_termios()
1393 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); in qcom_geni_serial_set_termios()
1394 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); in qcom_geni_serial_set_termios()
1408 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) in qcom_geni_console_setup()
1409 return -ENXIO; in qcom_geni_console_setup()
1411 port = get_port_from_line(co->index, true); in qcom_geni_console_setup()
1413 pr_err("Invalid line %d\n", co->index); in qcom_geni_console_setup()
1417 uport = &port->uport; in qcom_geni_console_setup()
1419 if (unlikely(!uport->membase)) in qcom_geni_console_setup()
1420 return -ENXIO; in qcom_geni_console_setup()
1422 if (!port->setup) { in qcom_geni_console_setup()
1437 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_write()
1439 __qcom_geni_serial_console_write(&dev->port, s, n); in qcom_geni_serial_earlycon_write()
1446 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_read()
1447 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_read()
1465 con->read = qcom_geni_serial_earlycon_read; in qcom_geni_serial_enable_early_read()
1477 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_setup()
1482 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ in qcom_geni_serial_earlycon_setup()
1486 if (!uport->membase) in qcom_geni_serial_earlycon_setup()
1487 return -EINVAL; in qcom_geni_serial_earlycon_setup()
1489 uport->private_data = &earlycon_private_data; in qcom_geni_serial_earlycon_setup()
1492 se.base = uport->membase; in qcom_geni_serial_earlycon_setup()
1494 return -ENXIO; in qcom_geni_serial_earlycon_setup()
1510 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); in qcom_geni_serial_earlycon_setup()
1513 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1514 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1515 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1516 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1517 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1518 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1519 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_earlycon_setup()
1521 dev->con->write = qcom_geni_serial_earlycon_write; in qcom_geni_serial_earlycon_setup()
1522 dev->con->setup = NULL; in qcom_geni_serial_earlycon_setup()
1523 qcom_geni_serial_enable_early_read(&se, dev->con); in qcom_geni_serial_earlycon_setup()
1527 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1546 .index = -1,
1585 geni_icc_enable(&port->se); in qcom_geni_serial_pm()
1586 if (port->clk_rate) in qcom_geni_serial_pm()
1587 dev_pm_opp_set_rate(uport->dev, port->clk_rate); in qcom_geni_serial_pm()
1588 geni_se_resources_on(&port->se); in qcom_geni_serial_pm()
1591 geni_se_resources_off(&port->se); in qcom_geni_serial_pm()
1592 dev_pm_opp_set_rate(uport->dev, 0); in qcom_geni_serial_pm()
1593 geni_icc_disable(&port->se); in qcom_geni_serial_pm()
1648 data = of_device_get_match_data(&pdev->dev); in qcom_geni_serial_probe()
1650 return -EINVAL; in qcom_geni_serial_probe()
1652 if (data->console) { in qcom_geni_serial_probe()
1654 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1657 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1658 if (line == -ENODEV) /* compat with non-standard aliases */ in qcom_geni_serial_probe()
1659 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); in qcom_geni_serial_probe()
1662 port = get_port_from_line(line, data->console); in qcom_geni_serial_probe()
1664 dev_err(&pdev->dev, "Invalid line %d\n", line); in qcom_geni_serial_probe()
1668 uport = &port->uport; in qcom_geni_serial_probe()
1670 if (uport->private_data) in qcom_geni_serial_probe()
1671 return -ENODEV; in qcom_geni_serial_probe()
1673 uport->dev = &pdev->dev; in qcom_geni_serial_probe()
1674 port->dev_data = data; in qcom_geni_serial_probe()
1675 port->se.dev = &pdev->dev; in qcom_geni_serial_probe()
1676 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); in qcom_geni_serial_probe()
1677 port->se.clk = devm_clk_get(&pdev->dev, "se"); in qcom_geni_serial_probe()
1678 if (IS_ERR(port->se.clk)) { in qcom_geni_serial_probe()
1679 ret = PTR_ERR(port->se.clk); in qcom_geni_serial_probe()
1680 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); in qcom_geni_serial_probe()
1686 return -EINVAL; in qcom_geni_serial_probe()
1687 uport->mapbase = res->start; in qcom_geni_serial_probe()
1689 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1690 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1691 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; in qcom_geni_serial_probe()
1693 if (!data->console) { in qcom_geni_serial_probe()
1694 port->rx_buf = devm_kzalloc(uport->dev, in qcom_geni_serial_probe()
1696 if (!port->rx_buf) in qcom_geni_serial_probe()
1697 return -ENOMEM; in qcom_geni_serial_probe()
1700 ret = geni_icc_get(&port->se, NULL); in qcom_geni_serial_probe()
1703 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1704 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1707 ret = geni_icc_set_bw(&port->se); in qcom_geni_serial_probe()
1711 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, in qcom_geni_serial_probe()
1713 uart_console(uport) ? "console" : "uart", uport->line); in qcom_geni_serial_probe()
1714 if (!port->name) in qcom_geni_serial_probe()
1715 return -ENOMEM; in qcom_geni_serial_probe()
1720 uport->irq = irq; in qcom_geni_serial_probe()
1721 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); in qcom_geni_serial_probe()
1723 if (!data->console) in qcom_geni_serial_probe()
1724 port->wakeup_irq = platform_get_irq_optional(pdev, 1); in qcom_geni_serial_probe()
1726 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) in qcom_geni_serial_probe()
1727 port->rx_tx_swap = true; in qcom_geni_serial_probe()
1729 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) in qcom_geni_serial_probe()
1730 port->cts_rts_swap = true; in qcom_geni_serial_probe()
1732 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); in qcom_geni_serial_probe()
1736 ret = devm_pm_opp_of_add_table(&pdev->dev); in qcom_geni_serial_probe()
1737 if (ret && ret != -ENODEV) { in qcom_geni_serial_probe()
1738 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in qcom_geni_serial_probe()
1742 port->private_data.drv = drv; in qcom_geni_serial_probe()
1743 uport->private_data = &port->private_data; in qcom_geni_serial_probe()
1746 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); in qcom_geni_serial_probe()
1747 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, in qcom_geni_serial_probe()
1748 IRQF_TRIGGER_HIGH, port->name, uport); in qcom_geni_serial_probe()
1750 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); in qcom_geni_serial_probe()
1758 if (port->wakeup_irq > 0) { in qcom_geni_serial_probe()
1759 device_init_wakeup(&pdev->dev, true); in qcom_geni_serial_probe()
1760 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in qcom_geni_serial_probe()
1761 port->wakeup_irq); in qcom_geni_serial_probe()
1763 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_probe()
1775 struct uart_driver *drv = port->private_data.drv; in qcom_geni_serial_remove()
1777 dev_pm_clear_wake_irq(&pdev->dev); in qcom_geni_serial_remove()
1778 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_remove()
1779 uart_remove_one_port(drv, &port->uport); in qcom_geni_serial_remove()
1785 struct uart_port *uport = &port->uport; in qcom_geni_serial_suspend()
1786 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_suspend()
1793 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); in qcom_geni_serial_suspend()
1794 geni_icc_set_bw(&port->se); in qcom_geni_serial_suspend()
1796 return uart_suspend_port(private_data->drv, uport); in qcom_geni_serial_suspend()
1803 struct uart_port *uport = &port->uport; in qcom_geni_serial_resume()
1804 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_resume()
1806 ret = uart_resume_port(private_data->drv, uport); in qcom_geni_serial_resume()
1808 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); in qcom_geni_serial_resume()
1809 geni_icc_set_bw(&port->se); in qcom_geni_serial_resume()
1830 .compatible = "qcom,geni-debug-uart",
1834 .compatible = "qcom,geni-uart",