Lines Matching +full:tx +full:- +full:sync +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
101 (void)readb(port->control_reg); in zssync()
108 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
110 #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
145 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
151 #define TxINT_ENAB 0x2 /* Tx Int Enable */
169 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
185 #define SYNC_ENAB 0 /* Sync Modes Enable */
191 #define MONSYNC 0 /* 8 Bit Sync character */
192 #define BISYNC 0x10 /* 16 bit sync character */
193 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
194 #define EXTSYNC 0x30 /* External Sync Mode */
196 #define X1CLK 0x0 /* x1 clock mode */
197 #define X16CLK 0x40 /* x16 clock mode */
198 #define X32CLK 0x80 /* x32 clock mode */
199 #define X64CLK 0xC0 /* x64 clock mode */
204 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
206 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
207 #define TxENABLE 0x8 /* Tx Enable */
209 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
210 #define Tx7 0x20 /* Tx 7 bits/character */
211 #define Tx6 0x40 /* Tx 6 bits/character */
212 #define Tx8 0x60 /* Tx 8 bits/character */
216 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
218 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
237 #define BIT6 1 /* 6 bit/8bit sync */
248 /* Write Register 11 (Clock Mode control) */
250 #define TRxCTC 1 /* TRxC = Transmit clock */
254 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
255 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
256 #define TCBR 0x10 /* Transmit clock = BR Generator output */
257 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
258 #define RCRTxCP 0 /* Receive clock = RTxC pin */
259 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
260 #define RCBR 0x40 /* Receive clock = BR Generator output */
261 #define RCDPLL 0x60 /* Receive clock = DPLL output */
275 #define RMC 0x40 /* Reset missing clock */
283 #define EN85C30 1 /* Enable some 85c30-enhanced registers */
287 #define SYNCIE 0x10 /* Sync/hunt IE */
289 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
296 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
298 #define SYNC_HUNT 0x10 /* Sync/hunt */
300 #define TxEOM 0x40 /* Tx underrun */
320 /* Read Register 2 (channel b only) - Interrupt vector */
333 #define CHBTxIP 0x2 /* Channel B Tx IP */
336 #define CHATxIP 0x10 /* Channel A Tx IP */
345 #define CLK1MIS 0x80 /* One clock missing */
361 #define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
362 #define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
363 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
364 #define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
365 #define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
366 #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
367 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
368 #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
369 #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
370 #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
371 #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)