30 #define OWL_UART_STAT	0x00c  macro
114 	stat = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_get_mctrl()
130 	val = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_tx_empty()
146 	val = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_stop_rx()
148 	owl_uart_write(port, val, OWL_UART_STAT);  in owl_uart_stop_rx()
159 	val = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_stop_tx()
161 	owl_uart_write(port, val, OWL_UART_STAT);  in owl_uart_stop_tx()
173 	val = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_start_tx()
175 	owl_uart_write(port, val, OWL_UART_STAT);  in owl_uart_start_tx()
187 		!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU),  in owl_uart_send_chars()
199 	stat = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_receive_chars()
226 		stat = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_receive_chars()
239 	stat = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_irq()
247 	stat = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_irq()
249 	owl_uart_write(port, stat, OWL_UART_STAT);  in owl_uart_irq()
286 	val = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_startup()
289 	owl_uart_write(port, val, OWL_UART_STAT);  in owl_uart_startup()
448 	if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)  in owl_uart_poll_get_char()
460 	ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,  in owl_uart_poll_put_char()
502 	while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)  in owl_console_putchar()
529 	while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)  in owl_uart_port_write()
533 	val = owl_uart_read(port, OWL_UART_STAT);  in owl_uart_port_write()
535 	owl_uart_write(port, val, OWL_UART_STAT);  in owl_uart_port_write()