Lines Matching refs:OWL_UART_CTL
27 #define OWL_UART_CTL 0x000 macro
98 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_set_mctrl()
105 owl_uart_write(port, ctl, OWL_UART_CTL); in owl_uart_set_mctrl()
113 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_get_mctrl()
142 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_stop_rx()
144 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_stop_rx()
155 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_stop_tx()
157 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_stop_tx()
177 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_start_tx()
179 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_start_tx()
195 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_receive_chars()
197 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_receive_chars()
263 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_shutdown()
266 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_shutdown()
291 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_startup()
294 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_startup()
318 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_set_termios()
361 owl_uart_write(port, ctl, OWL_UART_CTL); in owl_uart_set_termios()
520 old_ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_port_write()
524 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_port_write()
537 owl_uart_write(port, old_ctl, OWL_UART_CTL); in owl_uart_port_write()