129 	out_8(&psc->ctur, divisor >> 8);  in mpc52xx_set_divisor()
130 	out_8(&psc->ctlr, divisor & 0xff);  in mpc52xx_set_divisor()
145 	out_8(&PSC(port)->command, cmd);  in mpc52xx_psc_command()
150 	out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_set_mode()
151 	out_8(&PSC(port)->mode, mr1);  in mpc52xx_psc_set_mode()
152 	out_8(&PSC(port)->mode, mr2);  in mpc52xx_psc_set_mode()
158 		out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);  in mpc52xx_psc_set_rts()
160 		out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);  in mpc52xx_psc_set_rts()
170 	out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);  in mpc52xx_psc_enable_ms()
188 	out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_get_mr1()
199 	out_8(&fifo->rfcntl, 0x00);  in mpc52xx_psc_fifo_init()
201 	out_8(&fifo->tfcntl, 0x07);  in mpc52xx_psc_fifo_init()
270 	out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);  in mpc52xx_psc_write_char()
510 	out_8(&FIFO_512x(port)->txdata_8, c);  in mpc512x_psc_write_char()
766 	out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);  in mpc5125_psc_fifo_init()
848 	out_8(&FIFO_5125(port)->txdata_8, c);  in mpc5125_psc_write_char()
876 	out_8(&psc->mpc52xx_psc_clock_select, prescaler);  in mpc5125_set_divisor()
877 	out_8(&psc->ctur, divisor >> 8);  in mpc5125_set_divisor()
878 	out_8(&psc->ctlr, divisor & 0xff);  in mpc5125_set_divisor()
919 	out_8(&PSC_5125(port)->command, cmd);  in mpc5125_psc_command()
924 	out_8(&PSC_5125(port)->mr1, mr1);  in mpc5125_psc_set_mode()
925 	out_8(&PSC_5125(port)->mr2, mr2);  in mpc5125_psc_set_mode()
931 		out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);  in mpc5125_psc_set_rts()
933 		out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);  in mpc5125_psc_set_rts()
943 	out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);  in mpc5125_psc_enable_ms()