Lines Matching +full:tx +full:- +full:sync +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
111 #define MONSYNC 0 /* 8 Bit Sync character */
112 #define BISYNC 0x10 /* 16 bit sync character */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
118 #define X32CLK 0x80 /* x32 clock mode */
119 #define X64CLK 0xC0 /* x64 clock mode */
124 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
127 #define TxENAB 0x8 /* Tx Enable */
129 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
130 #define Tx7 0x20 /* Tx 7 bits/character */
131 #define Tx6 0x40 /* Tx 6 bits/character */
132 #define Tx8 0x60 /* Tx 8 bits/character */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
154 #define BIT6 1 /* 6 bit/8bit sync */
165 /* Write Register 11 (Clock Mode control) */
167 #define TRxCTC 1 /* TRxC = Transmit clock */
171 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
172 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
173 #define TCBR 0x10 /* Transmit clock = BR Generator output */
174 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
175 #define RCRTxCP 0 /* Receive clock = RTxC pin */
176 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
177 #define RCBR 0x40 /* Receive clock = BR Generator output */
178 #define RCDPLL 0x60 /* Receive clock = DPLL output */
192 #define RMC 0x40 /* Reset missing clock */
202 #define SYNCIE 0x10 /* Sync/hunt IE */
204 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
211 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
213 #define SYNC 0x10 /* Sync/hunt */ macro
215 #define TxEOM 0x40 /* Tx underrun */
235 /* Read Register 2 (channel b only) - Interrupt vector */
248 #define CHBTxIP 0x2 /* Channel B Tx IP */
251 #define CHATxIP 0x10 /* Channel A Tx IP */
260 #define CLK1MIS 0x80 /* One clock missing */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
277 readb(&channel->data); \
279 readb(&channel->data); \