Lines Matching +full:1 +full:br +full:- +full:10
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
40 #define R1 1
49 #define R10 10
69 /* Write Register 1 */
107 #define SB1 0x4 /* 1 stop bit/char */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
143 #define VIS 1 /* Vector Includes Status */
153 /* Write Register 10 (misc control bits) */
154 #define BIT6 1 /* 6 bit/8bit sync */
161 #define FM1 0x40 /* FM1 (transition = 1) */
167 #define TRxCTC 1 /* TRxC = Transmit clock */
168 #define TRxCBR 2 /* TRxC = BR Generator Output */
173 #define TCBR 0x10 /* Transmit clock = BR Generator output */
177 #define RCBR 0x40 /* Receive clock = BR Generator output */
186 #define BRENAB 1 /* Baud rate generator enable */
194 #define SSBR 0x80 /* Set DPLL source = BR generator */
218 /* Read Register 1 */
227 #define RES18 0xe /* 1/8 */
235 /* Read Register 2 (channel b only) - Interrupt vector */
256 /* Read Register 10 (misc status bits) */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
277 readb(&channel->data); \
279 readb(&channel->data); \