Lines Matching +full:inverted +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0+
31 #include <linux/dma-mapping.h>
34 #include <linux/dma/imx-dma.h>
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
162 /* We've been assigned a range on the "Low-density serial ports" major */
175 #define DRIVER_NAME "IMX-uart"
259 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
260 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
263 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
264 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
265 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
277 writel(val, sport->port.membase + offset); in imx_uart_writel()
282 return readl(sport->port.membase + offset); in imx_uart_readl()
287 return sport->devdata->uts_reg; in imx_uart_uts_reg()
292 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
303 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
304 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
305 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
312 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
313 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
314 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
323 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
332 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
351 * and UTS[6-3]". in imx_uart_soft_reset()
364 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
372 sport->idle_counter = 0; in imx_uart_soft_reset()
397 if (sport->dma_is_enabled) { in imx_uart_start_rx()
416 if (sport->tx_state == OFF) in imx_uart_stop_tx()
423 if (sport->dma_is_txing) in imx_uart_stop_tx()
440 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
441 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
442 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
444 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
445 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
446 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
453 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
454 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
457 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
460 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
466 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
469 sport->tx_state = OFF; in imx_uart_stop_tx()
472 sport->tx_state = OFF; in imx_uart_stop_tx()
486 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
497 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx_with_loopback_ctrl()
498 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx_with_loopback_ctrl()
499 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
515 * Stop RX and enable loopback in order to make sure RS485 bus in imx_uart_stop_rx()
526 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
528 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
536 struct tty_port *tport = &sport->port.state->port; in imx_uart_transmit_buffer()
539 if (sport->port.x_char) { in imx_uart_transmit_buffer()
541 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
542 sport->port.icount.tx++; in imx_uart_transmit_buffer()
543 sport->port.x_char = 0; in imx_uart_transmit_buffer()
547 if (kfifo_is_empty(&tport->xmit_fifo) || in imx_uart_transmit_buffer()
548 uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
549 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
553 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
556 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
561 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
573 uart_fifo_get(&sport->port, &c)) in imx_uart_transmit_buffer()
576 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in imx_uart_transmit_buffer()
577 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
579 if (kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_transmit_buffer()
580 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
586 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx_callback()
587 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
591 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_dma_tx_callback()
593 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
599 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
601 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
603 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
605 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in imx_uart_dma_tx_callback()
606 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
608 if (!kfifo_is_empty(&tport->xmit_fifo) && in imx_uart_dma_tx_callback()
609 !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
611 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
617 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_dma_tx_callback()
623 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx()
624 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
626 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
627 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
631 if (sport->dma_is_txing) in imx_uart_dma_tx()
638 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in imx_uart_dma_tx()
639 sport->tx_bytes = kfifo_len(&tport->xmit_fifo); in imx_uart_dma_tx()
640 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in imx_uart_dma_tx()
641 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes); in imx_uart_dma_tx()
643 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
651 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
656 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
657 desc->callback_param = sport; in imx_uart_dma_tx()
659 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes); in imx_uart_dma_tx()
666 sport->dma_is_txing = 1; in imx_uart_dma_tx()
676 struct tty_port *tport = &sport->port.state->port; in imx_uart_start_tx()
679 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_start_tx()
683 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
688 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
689 if (sport->tx_state == OFF) { in imx_uart_start_tx()
691 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
698 * Since we are about to transmit we can not stop RX in imx_uart_start_tx()
700 * transmitted data being just looped to RX. in imx_uart_start_tx()
702 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
703 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
706 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
708 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
709 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
710 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
717 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
718 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
720 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
725 * tx-callback. in imx_uart_start_tx()
727 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
733 sport->tx_state = SEND; in imx_uart_start_tx()
736 sport->tx_state = SEND; in imx_uart_start_tx()
739 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
744 if (sport->dma_is_enabled) { in imx_uart_start_tx()
745 if (sport->port.x_char) { in imx_uart_start_tx()
746 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
747 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
755 if (!kfifo_is_empty(&tport->xmit_fifo) && in imx_uart_start_tx()
770 * Update sport->old_status here, so any follow-up calls to in __imx_uart_rtsint()
781 sport->old_status |= TIOCM_CTS; in __imx_uart_rtsint()
783 sport->old_status &= ~TIOCM_CTS; in __imx_uart_rtsint()
784 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
785 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
795 uart_port_lock(&sport->port); in imx_uart_rtsint()
799 uart_port_unlock(&sport->port); in imx_uart_rtsint()
808 uart_port_lock(&sport->port); in imx_uart_txint()
810 uart_port_unlock(&sport->port); in imx_uart_txint()
814 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
815 * This is to be called from Rx ISRs only when some bytes were actually
822 * issuing soft reset to the UART (just stop/start of RX does not help). Note
830 /* To detect hardware 0xff flood we monitor RxD line between RX in imx_uart_check_flood()
836 * progress, so we might get RX interrupt later with USR2_WAKE bit in imx_uart_check_flood()
843 * We use 'idle_counter' to ensure that we got at least so many RX in imx_uart_check_flood()
850 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
855 sport->idle_counter = 0; in imx_uart_check_flood()
856 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
857 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
858 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
866 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
867 u32 usr2, rx; in __imx_uart_rxint() local
874 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { in __imx_uart_rxint()
876 sport->port.icount.rx++; in __imx_uart_rxint()
878 if (unlikely(rx & URXD_ERR)) { in __imx_uart_rxint()
879 if (rx & URXD_BRK) { in __imx_uart_rxint()
880 sport->port.icount.brk++; in __imx_uart_rxint()
881 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
884 else if (rx & URXD_PRERR) in __imx_uart_rxint()
885 sport->port.icount.parity++; in __imx_uart_rxint()
886 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
887 sport->port.icount.frame++; in __imx_uart_rxint()
888 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
889 sport->port.icount.overrun++; in __imx_uart_rxint()
891 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
894 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
896 if (rx & URXD_BRK) in __imx_uart_rxint()
898 else if (rx & URXD_PRERR) in __imx_uart_rxint()
900 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
902 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
905 sport->port.sysrq = 0; in __imx_uart_rxint()
906 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
910 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
913 if (tty_insert_flip_char(port, rx, flg) == 0) in __imx_uart_rxint()
914 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
927 uart_port_lock(&sport->port); in imx_uart_rxint()
931 uart_port_unlock(&sport->port); in imx_uart_rxint()
939 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
955 if (sport->dte_mode) in imx_uart_get_hwmctrl()
972 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
977 sport->old_status = status; in imx_uart_mctrl_check()
980 sport->port.icount.rng++; in imx_uart_mctrl_check()
982 sport->port.icount.dsr++; in imx_uart_mctrl_check()
984 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
986 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
988 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
997 uart_port_lock(&sport->port); in imx_uart_int()
1009 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
1062 sport->port.icount.overrun++; in imx_uart_int()
1067 uart_port_unlock(&sport->port); in imx_uart_int()
1083 if (sport->dma_is_txing) in imx_uart_tx_empty()
1095 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1106 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1119 * configured for CRTSCTS, so we use inverted UCR2_IRTS in imx_uart_set_mctrl()
1138 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1150 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_break_ctl()
1159 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_break_ctl()
1163 * This is our per-port timeout handler, for checking the
1171 if (sport->port.state) { in imx_uart_timeout()
1172 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_timeout()
1174 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_timeout()
1176 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1181 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1182 * [1] the RX DMA buffer is full.
1191 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1192 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1193 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1195 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1201 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1204 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1206 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1211 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1214 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1216 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1222 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1225 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1226 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1228 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1229 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1232 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1235 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1237 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1239 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1241 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1242 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1246 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1248 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1249 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1253 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1255 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1258 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1259 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1264 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1270 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1271 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1272 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1276 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1277 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1279 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1282 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1283 return -EINVAL; in imx_uart_start_rx_dma()
1287 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1292 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1293 return -EINVAL; in imx_uart_start_rx_dma()
1295 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1296 desc->callback_param = sport; in imx_uart_start_rx_dma()
1298 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1299 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1300 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1308 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1315 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1317 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1319 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1323 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1326 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1332 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1336 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1358 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1359 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1360 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1361 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1362 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1363 kfree(sport->rx_buf); in imx_uart_dma_exit()
1364 sport->rx_buf = NULL; in imx_uart_dma_exit()
1367 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1368 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1369 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1370 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1377 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1381 /* Prepare for RX : */ in imx_uart_dma_init()
1382 chan = dma_request_chan(dev, "rx"); in imx_uart_dma_init()
1385 sport->dma_chan_rx = NULL; in imx_uart_dma_init()
1389 sport->dma_chan_rx = chan; in imx_uart_dma_init()
1392 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1395 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1396 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1398 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1402 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1403 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1404 if (!sport->rx_buf) { in imx_uart_dma_init()
1405 ret = -ENOMEM; in imx_uart_dma_init()
1408 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1414 sport->dma_chan_tx = NULL; in imx_uart_dma_init()
1418 sport->dma_chan_tx = chan; in imx_uart_dma_init()
1421 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1424 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1448 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1462 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1465 /* half the RX buffer size */
1476 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1479 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1481 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1500 lockdep_set_subclass(&port->lock, 1); in imx_uart_startup()
1504 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_startup()
1517 if (sport->have_rtscts) in imx_uart_startup()
1525 if (sport->inverted_rx) in imx_uart_startup()
1533 if (sport->inverted_tx) in imx_uart_startup()
1539 if (sport->dte_mode) in imx_uart_startup()
1547 if (!sport->have_rtscts) in imx_uart_startup()
1550 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1560 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1577 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_startup()
1589 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1590 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1591 if (sport->dma_is_txing) { in imx_uart_shutdown()
1592 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1593 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1594 sport->dma_is_txing = 0; in imx_uart_shutdown()
1596 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1597 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1598 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1600 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1603 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1607 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1611 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1613 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1617 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1622 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1628 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1634 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1635 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1636 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1660 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND) in imx_uart_shutdown()
1673 loops = port->rs485.flags & SER_RS485_ENABLED ? in imx_uart_shutdown()
1674 port->rs485.delay_rts_after_send : 0; in imx_uart_shutdown()
1675 while (sport->tx_state != OFF && loops--) { in imx_uart_shutdown()
1676 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1678 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1681 if (sport->tx_state != OFF) { in imx_uart_shutdown()
1682 dev_warn(sport->port.dev, "unexpected tx_state %d\n", in imx_uart_shutdown()
1683 sport->tx_state); in imx_uart_shutdown()
1689 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_shutdown()
1691 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_shutdown()
1697 sport->tx_state = OFF; in imx_uart_shutdown()
1700 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1702 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1703 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1710 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1712 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1715 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1716 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1717 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1720 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1725 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1740 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1748 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1749 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1750 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1751 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1755 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1760 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1763 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_set_termios()
1773 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1776 if (!sport->have_rtscts) in imx_uart_set_termios()
1777 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1779 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1785 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1790 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1799 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1801 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1803 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1805 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1809 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1810 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1811 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1812 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1813 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1818 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1819 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1820 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1821 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1822 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1827 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1828 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1831 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1832 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1835 * Update the per-port timeout. in imx_uart_set_termios()
1837 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1839 /* custom-baudrate handling */ in imx_uart_set_termios()
1840 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1842 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1844 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1850 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1853 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1859 num -= 1; in imx_uart_set_termios()
1860 denom -= 1; in imx_uart_set_termios()
1883 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1888 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1889 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1891 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_set_termios()
1896 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1905 port->type = PORT_IMX; in imx_uart_config_port()
1918 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1919 ret = -EINVAL; in imx_uart_verify_port()
1920 if (port->irq != ser->irq) in imx_uart_verify_port()
1921 ret = -EINVAL; in imx_uart_verify_port()
1922 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1923 ret = -EINVAL; in imx_uart_verify_port()
1924 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1925 ret = -EINVAL; in imx_uart_verify_port()
1926 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1927 ret = -EINVAL; in imx_uart_verify_port()
1928 if (port->iobase != ser->port) in imx_uart_verify_port()
1929 ret = -EINVAL; in imx_uart_verify_port()
1930 if (ser->hub6 != 0) in imx_uart_verify_port()
1931 ret = -EINVAL; in imx_uart_verify_port()
1944 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1947 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1949 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1953 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_poll_init()
1958 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1981 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_poll_init()
2022 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
2023 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
2024 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
2025 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
2026 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
2030 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
2037 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
2038 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
2039 rs485conf->flags & SER_RS485_RX_DURING_TX) { in imx_uart_rs485_config()
2085 sport->last_putchar_was_newline = (ch == '\n'); in imx_uart_console_putchar()
2090 struct uart_port *up = &imx_uart_ports[co->index]->port; in imx_uart_console_device_lock()
2097 struct uart_port *up = &imx_uart_ports[co->index]->port; in imx_uart_console_device_unlock()
2105 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write_atomic()
2106 struct uart_port *port = &sport->port; in imx_uart_console_write_atomic()
2127 if (!sport->last_putchar_was_newline) in imx_uart_console_write_atomic()
2129 uart_console_write(port, wctxt->outbuf, wctxt->len, in imx_uart_console_write_atomic()
2146 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write_thread()
2147 struct uart_port *port = &sport->port; in imx_uart_console_write_thread()
2169 int len = READ_ONCE(wctxt->len); in imx_uart_console_write_thread()
2177 * actions (such as re-enabling the interrupts). in imx_uart_console_write_thread()
2179 * IMPORTANT: wctxt->outbuf and wctxt->len are no longer valid in imx_uart_console_write_thread()
2187 uart_console_write(port, wctxt->outbuf + i, 1, in imx_uart_console_write_thread()
2246 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2248 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2267 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2287 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2288 co->index = 0; in imx_uart_console_setup()
2289 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2291 return -ENODEV; in imx_uart_console_setup()
2294 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2298 sport->last_putchar_was_newline = true; in imx_uart_console_setup()
2307 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2310 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2314 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2316 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2325 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2327 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2328 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2344 .index = -1,
2369 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_start_tx()
2370 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2371 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2372 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_start_tx()
2382 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_stop_tx()
2383 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2384 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2385 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_stop_tx()
2397 /* Default RX DMA buffer configuration */
2403 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2412 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2414 return -ENOMEM; in imx_uart_probe()
2416 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2420 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2423 sport->port.line = ret; in imx_uart_probe()
2425 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2426 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2428 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2430 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2432 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2434 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2436 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2437 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2438 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2440 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2441 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2444 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2445 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2446 sport->port.line); in imx_uart_probe()
2447 return -EINVAL; in imx_uart_probe()
2460 sport->port.dev = &pdev->dev; in imx_uart_probe()
2461 sport->port.mapbase = res->start; in imx_uart_probe()
2462 sport->port.membase = base; in imx_uart_probe()
2463 sport->port.type = PORT_IMX; in imx_uart_probe()
2464 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2465 sport->port.irq = rxirq; in imx_uart_probe()
2466 sport->port.fifosize = 32; in imx_uart_probe()
2467 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2468 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2469 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2471 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2472 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2473 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2474 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2476 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2477 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2478 return PTR_ERR(sport->gpios); in imx_uart_probe()
2480 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2481 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2482 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2483 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2487 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2488 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2489 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2490 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2494 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2497 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2499 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); in imx_uart_probe()
2503 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2512 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2513 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2514 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2515 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2516 dev_err(&pdev->dev, in imx_uart_probe()
2517 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2534 * data from being fed into the RX FIFO, enable loopback mode in in imx_uart_probe()
2535 * UTS register, which disconnects the RX path from external RXD in imx_uart_probe()
2537 * no data can be fed to the RX FIFO that way. in imx_uart_probe()
2539 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2540 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2554 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2585 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2586 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2587 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2588 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2595 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2596 dev_name(&pdev->dev), sport); in imx_uart_probe()
2598 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2603 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2604 dev_name(&pdev->dev), sport); in imx_uart_probe()
2606 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2611 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2612 dev_name(&pdev->dev), sport); in imx_uart_probe()
2614 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2619 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2620 dev_name(&pdev->dev), sport); in imx_uart_probe()
2622 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2627 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2631 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2634 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2643 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2650 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_restore_context()
2651 if (!sport->context_saved) { in imx_uart_restore_context()
2652 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2656 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2657 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2658 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2659 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2660 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2661 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2662 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2663 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2664 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2665 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2666 sport->context_saved = false; in imx_uart_restore_context()
2667 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2675 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_save_context()
2676 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2677 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2678 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2679 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2680 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2681 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2682 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2683 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2684 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2685 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2686 sport->context_saved = true; in imx_uart_save_context()
2687 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_save_context()
2695 uart_port_lock_irq(&sport->port); in imx_uart_enable_wakeup()
2706 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2717 uart_port_unlock_irq(&sport->port); in imx_uart_enable_wakeup()
2726 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2740 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2754 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2755 disable_irq(sport->port.irq); in imx_uart_suspend()
2757 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2774 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2775 enable_irq(sport->port.irq); in imx_uart_resume()
2777 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2786 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2788 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2795 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2797 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2820 .name = "imx-uart",
2852 MODULE_ALIAS("platform:imx-uart");