Lines Matching +full:dcd +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0+
31 #include <linux/dma-mapping.h>
34 #include <linux/dma/imx-dma.h>
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
162 /* We've been assigned a range on the "Low-density serial ports" major */
175 #define DRIVER_NAME "IMX-uart"
211 struct mctrl_gpios *gpios; member
260 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
261 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
264 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
265 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
266 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
278 writel(val, sport->port.membase + offset); in imx_uart_writel()
283 return readl(sport->port.membase + offset); in imx_uart_readl()
288 return sport->devdata->uts_reg; in imx_uart_uts_reg()
293 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
304 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
305 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
306 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
313 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
314 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
315 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
324 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
333 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
352 * and UTS[6-3]". in imx_uart_soft_reset()
365 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
373 sport->idle_counter = 0; in imx_uart_soft_reset()
398 if (sport->dma_is_enabled) { in imx_uart_start_rx()
417 if (sport->tx_state == OFF) in imx_uart_stop_tx()
424 if (sport->dma_is_txing) in imx_uart_stop_tx()
441 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
442 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
443 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
445 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
446 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
447 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
454 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
455 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
458 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
461 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
467 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
470 sport->tx_state = OFF; in imx_uart_stop_tx()
473 sport->tx_state = OFF; in imx_uart_stop_tx()
487 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
498 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx_with_loopback_ctrl()
499 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx_with_loopback_ctrl()
500 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
527 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
529 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
537 struct tty_port *tport = &sport->port.state->port; in imx_uart_transmit_buffer()
540 if (sport->port.x_char) { in imx_uart_transmit_buffer()
542 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
543 sport->port.icount.tx++; in imx_uart_transmit_buffer()
544 sport->port.x_char = 0; in imx_uart_transmit_buffer()
548 if (kfifo_is_empty(&tport->xmit_fifo) || in imx_uart_transmit_buffer()
549 uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
550 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
554 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
557 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
562 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
574 uart_fifo_get(&sport->port, &c)) in imx_uart_transmit_buffer()
577 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in imx_uart_transmit_buffer()
578 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
580 if (kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_transmit_buffer()
581 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
587 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx_callback()
588 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
592 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_dma_tx_callback()
594 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
600 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
602 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
604 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
606 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in imx_uart_dma_tx_callback()
607 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
609 if (!kfifo_is_empty(&tport->xmit_fifo) && in imx_uart_dma_tx_callback()
610 !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
612 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
618 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_dma_tx_callback()
624 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx()
625 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
627 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
628 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
632 if (sport->dma_is_txing) in imx_uart_dma_tx()
639 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in imx_uart_dma_tx()
640 sport->tx_bytes = kfifo_len(&tport->xmit_fifo); in imx_uart_dma_tx()
641 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in imx_uart_dma_tx()
642 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes); in imx_uart_dma_tx()
644 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
652 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
657 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
658 desc->callback_param = sport; in imx_uart_dma_tx()
660 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes); in imx_uart_dma_tx()
667 sport->dma_is_txing = 1; in imx_uart_dma_tx()
677 struct tty_port *tport = &sport->port.state->port; in imx_uart_start_tx()
680 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_start_tx()
684 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
689 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
690 if (sport->tx_state == OFF) { in imx_uart_start_tx()
692 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
703 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
704 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
707 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
709 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
710 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
711 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
718 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
719 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
721 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
726 * tx-callback. in imx_uart_start_tx()
728 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
734 sport->tx_state = SEND; in imx_uart_start_tx()
737 sport->tx_state = SEND; in imx_uart_start_tx()
740 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
745 if (sport->dma_is_enabled) { in imx_uart_start_tx()
746 if (sport->port.x_char) { in imx_uart_start_tx()
747 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
748 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
756 if (!kfifo_is_empty(&tport->xmit_fifo) && in imx_uart_start_tx()
771 * Update sport->old_status here, so any follow-up calls to in __imx_uart_rtsint()
782 sport->old_status |= TIOCM_CTS; in __imx_uart_rtsint()
784 sport->old_status &= ~TIOCM_CTS; in __imx_uart_rtsint()
785 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
786 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
796 uart_port_lock(&sport->port); in imx_uart_rtsint()
800 uart_port_unlock(&sport->port); in imx_uart_rtsint()
809 uart_port_lock(&sport->port); in imx_uart_txint()
811 uart_port_unlock(&sport->port); in imx_uart_txint()
851 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
856 sport->idle_counter = 0; in imx_uart_check_flood()
857 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
858 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
859 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
867 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
877 sport->port.icount.rx++; in __imx_uart_rxint()
881 sport->port.icount.brk++; in __imx_uart_rxint()
882 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
886 sport->port.icount.parity++; in __imx_uart_rxint()
888 sport->port.icount.frame++; in __imx_uart_rxint()
890 sport->port.icount.overrun++; in __imx_uart_rxint()
892 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
895 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
906 sport->port.sysrq = 0; in __imx_uart_rxint()
907 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
911 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
915 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
928 uart_port_lock(&sport->port); in imx_uart_rxint()
932 uart_port_unlock(&sport->port); in imx_uart_rxint()
956 if (sport->dte_mode) in imx_uart_get_hwmctrl()
973 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
978 sport->old_status = status; in imx_uart_mctrl_check()
981 sport->port.icount.rng++; in imx_uart_mctrl_check()
983 sport->port.icount.dsr++; in imx_uart_mctrl_check()
985 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
987 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
989 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
998 uart_port_lock(&sport->port); in imx_uart_int()
1063 sport->port.icount.overrun++; in imx_uart_int()
1068 uart_port_unlock(&sport->port); in imx_uart_int()
1084 if (sport->dma_is_txing) in imx_uart_tx_empty()
1096 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1107 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1139 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1151 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_break_ctl()
1160 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_break_ctl()
1164 * This is our per-port timeout handler, for checking the
1172 if (sport->port.state) { in imx_uart_timeout()
1173 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_timeout()
1175 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_timeout()
1177 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1192 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1193 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1194 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1196 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1202 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1205 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1207 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1212 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1215 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1217 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1223 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1226 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1227 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1229 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1230 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1233 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1236 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1238 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1240 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1243 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1247 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1250 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1254 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1256 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1259 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1260 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1265 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1271 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1272 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1273 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1277 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1278 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1280 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1284 return -EINVAL; in imx_uart_start_rx_dma()
1288 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1294 return -EINVAL; in imx_uart_start_rx_dma()
1296 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1297 desc->callback_param = sport; in imx_uart_start_rx_dma()
1300 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1301 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1309 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1316 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1318 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1320 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1324 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1327 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1333 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1337 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1360 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1361 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1362 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1363 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1364 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1365 kfree(sport->rx_buf); in imx_uart_dma_exit()
1366 sport->rx_buf = NULL; in imx_uart_dma_exit()
1369 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1370 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1371 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1372 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1379 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1387 sport->dma_chan_rx = NULL; in imx_uart_dma_init()
1391 sport->dma_chan_rx = chan; in imx_uart_dma_init()
1394 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1397 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1398 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1404 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1405 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1406 if (!sport->rx_buf) { in imx_uart_dma_init()
1407 ret = -ENOMEM; in imx_uart_dma_init()
1410 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1416 sport->dma_chan_tx = NULL; in imx_uart_dma_init()
1420 sport->dma_chan_tx = chan; in imx_uart_dma_init()
1423 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1426 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1450 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1462 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_disable_dma()
1464 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1478 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1481 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1483 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1487 if (uart_console(&sport->port)) in imx_uart_startup()
1488 sport->rxtl = RXTL_CONSOLE_DEFAULT; in imx_uart_startup()
1490 sport->rxtl = RXTL_DEFAULT; in imx_uart_startup()
1492 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_startup()
1507 lockdep_set_subclass(&port->lock, 1); in imx_uart_startup()
1511 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_startup()
1524 if (sport->have_rtscts) in imx_uart_startup()
1532 if (sport->inverted_rx) in imx_uart_startup()
1540 if (sport->inverted_tx) in imx_uart_startup()
1546 if (sport->dte_mode) in imx_uart_startup()
1554 if (!sport->have_rtscts) in imx_uart_startup()
1557 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1567 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1584 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_startup()
1596 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1597 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1598 if (sport->dma_is_txing) { in imx_uart_shutdown()
1599 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1600 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1601 sport->dma_is_txing = 0; in imx_uart_shutdown()
1603 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1604 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1605 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1607 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1610 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1614 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1618 mctrl_gpio_disable_ms_sync(sport->gpios); in imx_uart_shutdown()
1620 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1624 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1629 timer_delete_sync(&sport->timer); in imx_uart_shutdown()
1635 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1641 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1642 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1643 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1667 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND) in imx_uart_shutdown()
1680 loops = port->rs485.flags & SER_RS485_ENABLED ? in imx_uart_shutdown()
1681 port->rs485.delay_rts_after_send : 0; in imx_uart_shutdown()
1682 while (sport->tx_state != OFF && loops--) { in imx_uart_shutdown()
1683 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1685 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1688 if (sport->tx_state != OFF) { in imx_uart_shutdown()
1689 dev_warn(sport->port.dev, "unexpected tx_state %d\n", in imx_uart_shutdown()
1690 sport->tx_state); in imx_uart_shutdown()
1696 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_shutdown()
1698 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_shutdown()
1704 sport->tx_state = OFF; in imx_uart_shutdown()
1707 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1709 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1710 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1717 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1719 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1722 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1723 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1724 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1727 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1732 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1747 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1755 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1756 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1757 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1758 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1762 timer_delete_sync(&sport->timer); in imx_uart_set_termios()
1767 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1770 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_set_termios()
1780 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1783 if (!sport->have_rtscts) in imx_uart_set_termios()
1784 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1786 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1792 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1797 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1806 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1808 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1810 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1812 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1816 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1817 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1818 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1819 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1820 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1825 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1826 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1827 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1828 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1829 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1834 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1835 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1838 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1839 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1842 * Update the per-port timeout. in imx_uart_set_termios()
1844 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1846 /* custom-baudrate handling */ in imx_uart_set_termios()
1847 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1849 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1851 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1857 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1860 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1866 num -= 1; in imx_uart_set_termios()
1867 denom -= 1; in imx_uart_set_termios()
1890 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1895 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1896 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1898 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_set_termios()
1903 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1912 port->type = PORT_IMX; in imx_uart_config_port()
1925 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1926 ret = -EINVAL; in imx_uart_verify_port()
1927 if (port->irq != ser->irq) in imx_uart_verify_port()
1928 ret = -EINVAL; in imx_uart_verify_port()
1929 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1930 ret = -EINVAL; in imx_uart_verify_port()
1931 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1932 ret = -EINVAL; in imx_uart_verify_port()
1933 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1934 ret = -EINVAL; in imx_uart_verify_port()
1935 if (port->iobase != ser->port) in imx_uart_verify_port()
1936 ret = -EINVAL; in imx_uart_verify_port()
1937 if (ser->hub6 != 0) in imx_uart_verify_port()
1938 ret = -EINVAL; in imx_uart_verify_port()
1951 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1954 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1956 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1958 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_poll_init()
1960 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_poll_init()
1988 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_poll_init()
2029 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
2030 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
2031 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
2032 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
2033 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
2037 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
2045 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
2046 rs485conf->flags & SER_RS485_RX_DURING_TX) { in imx_uart_rs485_config()
2050 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_rs485_config()
2092 sport->last_putchar_was_newline = (ch == '\n'); in imx_uart_console_putchar()
2097 struct uart_port *up = &imx_uart_ports[co->index]->port; in imx_uart_console_device_lock()
2104 struct uart_port *up = &imx_uart_ports[co->index]->port; in imx_uart_console_device_unlock()
2112 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write_atomic()
2113 struct uart_port *port = &sport->port; in imx_uart_console_write_atomic()
2134 if (!sport->last_putchar_was_newline) in imx_uart_console_write_atomic()
2136 uart_console_write(port, wctxt->outbuf, wctxt->len, in imx_uart_console_write_atomic()
2153 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write_thread()
2154 struct uart_port *port = &sport->port; in imx_uart_console_write_thread()
2176 int len = READ_ONCE(wctxt->len); in imx_uart_console_write_thread()
2184 * actions (such as re-enabling the interrupts). in imx_uart_console_write_thread()
2186 * IMPORTANT: wctxt->outbuf and wctxt->len are no longer valid in imx_uart_console_write_thread()
2194 uart_console_write(port, wctxt->outbuf + i, 1, in imx_uart_console_write_thread()
2253 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2255 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2274 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2294 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2295 co->index = 0; in imx_uart_console_setup()
2296 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2298 return -ENODEV; in imx_uart_console_setup()
2301 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2305 sport->last_putchar_was_newline = true; in imx_uart_console_setup()
2312 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_console_setup()
2314 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2317 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2321 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2323 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2332 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2334 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2335 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2351 .index = -1,
2376 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_start_tx()
2377 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2378 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2379 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_start_tx()
2389 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_stop_tx()
2390 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2391 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2392 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_stop_tx()
2410 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2419 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2421 return -ENOMEM; in imx_uart_probe()
2423 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2427 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2430 sport->port.line = ret; in imx_uart_probe()
2432 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2433 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2435 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2437 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2439 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2441 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2443 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2444 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2445 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2447 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2448 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2451 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2452 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2453 sport->port.line); in imx_uart_probe()
2454 return -EINVAL; in imx_uart_probe()
2467 sport->port.dev = &pdev->dev; in imx_uart_probe()
2468 sport->port.mapbase = res->start; in imx_uart_probe()
2469 sport->port.membase = base; in imx_uart_probe()
2470 sport->port.type = PORT_IMX; in imx_uart_probe()
2471 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2472 sport->port.irq = rxirq; in imx_uart_probe()
2473 sport->port.fifosize = 32; in imx_uart_probe()
2474 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2475 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2476 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2478 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2479 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2480 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2481 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2483 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2484 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2485 return PTR_ERR(sport->gpios); in imx_uart_probe()
2487 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2488 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2489 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2490 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2494 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2495 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2496 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2497 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2501 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2504 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2506 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); in imx_uart_probe()
2510 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2519 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2520 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2521 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2522 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2523 dev_err(&pdev->dev, in imx_uart_probe()
2524 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2546 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2547 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2561 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2563 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI in imx_uart_probe()
2565 * and DCD (when they are outputs) or enables the respective in imx_uart_probe()
2592 hrtimer_setup(&sport->trigger_start_tx, imx_trigger_start_tx, CLOCK_MONOTONIC, in imx_uart_probe()
2594 hrtimer_setup(&sport->trigger_stop_tx, imx_trigger_stop_tx, CLOCK_MONOTONIC, in imx_uart_probe()
2602 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2603 dev_name(&pdev->dev), sport); in imx_uart_probe()
2605 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2610 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2611 dev_name(&pdev->dev), sport); in imx_uart_probe()
2613 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2618 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2619 dev_name(&pdev->dev), sport); in imx_uart_probe()
2621 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2626 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2627 dev_name(&pdev->dev), sport); in imx_uart_probe()
2629 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2634 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2638 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2641 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2650 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2657 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_restore_context()
2658 if (!sport->context_saved) { in imx_uart_restore_context()
2659 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2663 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2664 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2665 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2666 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2667 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2668 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2669 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2670 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2671 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2672 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2673 sport->context_saved = false; in imx_uart_restore_context()
2674 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2682 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_save_context()
2683 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2684 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2685 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2686 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2687 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2688 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2689 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2690 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2691 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2692 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2693 sport->context_saved = true; in imx_uart_save_context()
2694 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_save_context()
2702 uart_port_lock_irq(&sport->port); in imx_uart_enable_wakeup()
2713 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2724 uart_port_unlock_irq(&sport->port); in imx_uart_enable_wakeup()
2733 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2747 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2761 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2762 disable_irq(sport->port.irq); in imx_uart_suspend()
2764 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2781 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2782 enable_irq(sport->port.irq); in imx_uart_resume()
2784 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2793 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2795 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2802 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2804 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2827 .name = "imx-uart",
2859 MODULE_ALIAS("platform:imx-uart");