Lines Matching +full:vf610 +full:- +full:lpuart
1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale lpuart serial port driver
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
124 /* 32-bit register definition */
246 #define DRIVER_NAME "fsl-lpuart"
250 /* IMX lpuart has four extra unused regs located at the beginning */
349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
351 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
352 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
353 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, },
354 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
355 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
365 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
366 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
371 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
376 return sport->devtype == IMX8ULP_LPUART; in is_imx8ulp_lpuart()
381 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
386 switch (port->iotype) { in lpuart32_read()
388 return readl(port->membase + off); in lpuart32_read()
390 return ioread32be(port->membase + off); in lpuart32_read()
399 switch (port->iotype) { in lpuart32_write()
401 writel(val, port->membase + off); in lpuart32_write()
404 iowrite32be(val, port->membase + off); in lpuart32_write()
414 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
418 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
420 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
424 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
425 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
434 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
436 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
446 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
448 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
464 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
465 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
478 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx()
479 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
480 struct device *dev = sport->port.dev; in lpuart_dma_tx()
481 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
484 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
487 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in lpuart_dma_tx()
488 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); in lpuart_dma_tx()
489 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in lpuart_dma_tx()
490 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); in lpuart_dma_tx()
492 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
499 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
502 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
503 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
509 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
510 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
511 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
512 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
518 return kfifo_is_empty(&port->state->port.xmit_fifo) || in lpuart_stopped_or_empty()
525 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
526 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx_complete()
527 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
530 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
531 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
532 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
536 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
539 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); in lpuart_dma_tx_complete()
540 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
541 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
543 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in lpuart_dma_tx_complete()
544 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
546 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
547 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
551 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
553 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
556 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
561 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
563 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
565 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
567 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
581 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
584 dev_err(sport->port.dev, in lpuart_dma_tx_request()
594 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
595 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
601 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
604 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
605 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
606 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
607 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
608 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
614 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
616 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
618 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
620 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
627 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
647 sport->port.fifosize = 0; in lpuart_poll_init()
649 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_poll_init()
651 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
653 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
656 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
660 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
663 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
664 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
665 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
668 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
669 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
672 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
673 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_poll_init()
682 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
687 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
690 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
699 sport->port.fifosize = 0; in lpuart32_poll_init()
701 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_poll_init()
704 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
706 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
709 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
712 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
715 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
716 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
717 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
721 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
722 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_poll_init()
744 struct uart_port *port = &sport->port; in lpuart_transmit_buffer()
748 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, in lpuart_transmit_buffer()
749 writeb(ch, port->membase + UARTDR)); in lpuart_transmit_buffer()
754 struct tty_port *tport = &sport->port.state->port; in lpuart32_transmit_buffer()
758 if (sport->port.x_char) { in lpuart32_transmit_buffer()
759 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
760 sport->port.icount.tx++; in lpuart32_transmit_buffer()
761 sport->port.x_char = 0; in lpuart32_transmit_buffer()
765 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
766 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
770 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
773 while (txcnt < sport->txfifo_size && in lpuart32_transmit_buffer()
774 uart_fifo_get(&sport->port, &c)) { in lpuart32_transmit_buffer()
775 lpuart32_write(&sport->port, c, UARTDATA); in lpuart32_transmit_buffer()
776 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
781 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in lpuart32_transmit_buffer()
782 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
784 if (kfifo_is_empty(&tport->xmit_fifo)) in lpuart32_transmit_buffer()
785 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
794 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
795 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
797 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
801 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
811 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
828 pm_runtime_mark_last_busy(port->dev); in lpuart_uart_pm()
829 pm_runtime_put_autosuspend(port->dev); in lpuart_uart_pm()
832 pm_runtime_get_sync(port->dev); in lpuart_uart_pm()
842 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
843 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
845 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
862 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
866 * LPUART Transmission Complete Flag may never be set while queuing a break in lpuart32_tx_empty()
878 uart_port_lock(&sport->port); in lpuart_txint()
880 uart_port_unlock(&sport->port); in lpuart_txint()
886 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
889 uart_port_lock(&sport->port); in lpuart_rxint()
891 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
893 sport->port.icount.rx++; in lpuart_rxint()
898 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
899 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
901 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
906 sport->port.icount.parity++; in lpuart_rxint()
908 sport->port.icount.frame++; in lpuart_rxint()
913 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
919 sr &= sport->port.read_status_mask; in lpuart_rxint()
929 sport->port.sysrq = 0; in lpuart_rxint()
933 sport->port.icount.buf_overrun++; in lpuart_rxint()
938 sport->port.icount.overrun += overrun; in lpuart_rxint()
944 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
945 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
948 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
955 uart_port_lock(&sport->port); in lpuart32_txint()
957 uart_port_unlock(&sport->port); in lpuart32_txint()
963 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
967 uart_port_lock(&sport->port); in lpuart32_rxint()
969 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
971 sport->port.icount.rx++; in lpuart32_rxint()
976 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
977 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
981 * The LPUART can't distinguish between a break and a framing error, in lpuart32_rxint()
986 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
989 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
994 sport->port.icount.parity++; in lpuart32_rxint()
997 sport->port.icount.brk++; in lpuart32_rxint()
999 sport->port.icount.frame++; in lpuart32_rxint()
1003 sport->port.icount.overrun++; in lpuart32_rxint()
1005 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
1011 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1026 if (sport->is_cs7) in lpuart32_rxint()
1030 sport->port.icount.buf_overrun++; in lpuart32_rxint()
1034 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1044 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1047 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1048 readb(sport->port.membase + UARTDR); in lpuart_int()
1049 uart_handle_break(&sport->port); in lpuart_int()
1051 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1055 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1058 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1067 while (count--) { in lpuart_handle_sysrq_chars()
1076 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1079 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1080 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1081 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1082 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1083 ring->tail = 0; in lpuart_handle_sysrq()
1086 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1087 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1088 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1089 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1090 ring->tail = ring->head; in lpuart_handle_sysrq()
1107 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1110 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1111 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1116 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1120 lpuart32_write(&sport->port, sr, UARTSTAT); in lpuart_copy_rx_to_tty()
1123 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1125 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1128 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1134 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1136 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1139 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1142 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1144 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1154 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1157 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1159 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1163 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1167 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1169 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_copy_rx_to_tty()
1171 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1173 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1174 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1179 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1183 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1184 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1189 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1190 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1195 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1201 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1203 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1205 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1206 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1212 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1213 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1215 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1216 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1218 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1219 ring->tail = 0; in lpuart_copy_rx_to_tty()
1220 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1224 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1225 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1226 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1227 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1229 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1230 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1231 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1232 ring->head = 0; in lpuart_copy_rx_to_tty()
1233 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1234 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1237 sport->last_residue = state.residue; in lpuart_copy_rx_to_tty()
1240 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1243 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1246 if (!sport->dma_idle_int) in lpuart_copy_rx_to_tty()
1247 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1260 struct dma_chan *chan = sport->dma_rx_chan; in lpuart32_dma_idleint()
1261 struct circ_buf *ring = &sport->rx_ring; in lpuart32_dma_idleint()
1265 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart32_dma_idleint()
1267 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart32_dma_idleint()
1271 ring->head = sport->rx_sgl.length - state.residue; in lpuart32_dma_idleint()
1272 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart32_dma_idleint()
1284 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1285 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1288 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1291 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1294 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) in lpuart32_int()
1297 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1312 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_timer_func()
1313 struct circ_buf *ring = &sport->rx_ring; in lpuart_timer_func()
1318 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_timer_func()
1320 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_timer_func()
1324 ring->head = sport->rx_sgl.length - state.residue; in lpuart_timer_func()
1325 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart_timer_func()
1328 if ((count != 0) && (sport->last_residue == state.residue)) in lpuart_timer_func()
1331 mod_timer(&sport->lpuart_timer, in lpuart_timer_func()
1332 jiffies + sport->dma_rx_timeout); in lpuart_timer_func()
1334 if (uart_port_trylock_irqsave(&sport->port, &flags)) { in lpuart_timer_func()
1335 sport->last_residue = state.residue; in lpuart_timer_func()
1336 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_timer_func()
1343 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1345 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1346 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1347 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1348 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1349 unsigned int bits = tty_get_frame_size(termios->c_cflag); in lpuart_start_rx_dma()
1356 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1357 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); in lpuart_start_rx_dma()
1358 sport->rx_dma_rng_buf_len = max_t(int, in lpuart_start_rx_dma()
1359 sport->rxfifo_size * 2, in lpuart_start_rx_dma()
1360 sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1365 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1366 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1368 sport->last_residue = 0; in lpuart_start_rx_dma()
1369 sport->dma_rx_timeout = max(nsecs_to_jiffies( in lpuart_start_rx_dma()
1370 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); in lpuart_start_rx_dma()
1372 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1373 if (!ring->buf) in lpuart_start_rx_dma()
1374 return -ENOMEM; in lpuart_start_rx_dma()
1376 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1377 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1381 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1382 return -EINVAL; in lpuart_start_rx_dma()
1392 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1397 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1398 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1399 sport->rx_sgl.length, in lpuart_start_rx_dma()
1400 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1403 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1404 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1405 return -EFAULT; in lpuart_start_rx_dma()
1408 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1409 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1410 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1414 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1416 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1418 if (sport->dma_idle_int) { in lpuart_start_rx_dma()
1419 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart_start_rx_dma()
1421 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); in lpuart_start_rx_dma()
1424 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1425 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1435 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1438 if (!sport->dma_idle_int) in lpuart_dma_rx_free()
1439 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_rx_free()
1441 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1442 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1443 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1444 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1445 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1446 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1455 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1457 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1459 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1460 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1469 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1471 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1475 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1485 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1487 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1489 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1490 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1499 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1501 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1505 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1514 reg = readb(port->membase + UARTCR1); in lpuart_get_mctrl()
1537 reg = readb(port->membase + UARTCR1); in lpuart_set_mctrl()
1544 writeb(reg, port->membase + UARTCR1); in lpuart_set_mctrl()
1565 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1570 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1580 * LPUART IP now has two known bugs, one is CTS has higher priority than the in lpuart32_break_ctl()
1584 * Another bug is i.MX8QM LPUART may have an additional break character in lpuart32_break_ctl()
1599 /* Disable the TXINV to turn off break and re-enable transmitter. */ in lpuart32_break_ctl()
1612 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1616 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1618 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1620 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1624 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1627 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1628 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1629 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1632 if (uart_console(&sport->port)) in lpuart_setup_watermark()
1633 sport->rx_watermark = 1; in lpuart_setup_watermark()
1634 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1635 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1638 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1647 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1649 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1657 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1661 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1664 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1668 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1671 if (uart_console(&sport->port)) in lpuart32_setup_watermark()
1672 sport->rx_watermark = 1; in lpuart32_setup_watermark()
1673 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | in lpuart32_setup_watermark()
1675 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1678 if (!uart_console(&sport->port)) { in lpuart32_setup_watermark()
1679 val = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_setup_watermark()
1680 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); in lpuart32_setup_watermark()
1681 lpuart32_write(&sport->port, val, UARTMODIR); in lpuart32_setup_watermark()
1685 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1694 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1697 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1702 if (sport->dma_idle_int) in rx_dma_timer_init()
1705 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1706 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1707 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1712 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1713 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1714 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1716 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1717 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1720 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1721 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1722 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1724 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1725 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1734 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1737 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1740 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1744 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1745 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1747 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1748 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1751 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1752 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1758 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1766 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1769 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1773 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1779 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1780 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1782 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1785 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1786 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1788 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1794 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1801 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_hw_setup()
1808 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_hw_setup()
1817 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1819 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1821 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1823 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1836 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_hw_disable()
1839 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_hw_disable()
1846 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1847 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1849 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1851 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1858 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_hw_setup()
1868 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_hw_setup()
1877 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1879 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1881 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1883 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1892 sport->rxfifo_size = 16; in lpuart32_startup()
1893 sport->txfifo_size = 16; in lpuart32_startup()
1894 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1905 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1906 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1907 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1910 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1911 if (wait_event_interruptible_timeout(sport->dma_wait, in lpuart_dma_shutdown()
1912 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { in lpuart_dma_shutdown()
1913 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1914 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_dma_shutdown()
1916 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1919 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1920 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1921 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1922 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1934 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1937 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1954 temp = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_shutdown()
1955 lpuart32_write(&sport->port, temp, UARTSTAT); in lpuart32_shutdown()
1981 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1984 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1985 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1986 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1987 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1988 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1989 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1993 * - (7,e/o,1) in lpuart_set_termios()
1994 * - (8,n,1) in lpuart_set_termios()
1995 * - (8,m/s,1) in lpuart_set_termios()
1996 * - (8,e/o,1) in lpuart_set_termios()
1998 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
1999 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
2000 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2001 termios->c_cflag |= old_csize; in lpuart_set_termios()
2005 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
2006 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2009 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2010 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
2011 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2012 termios->c_cflag |= CS8; in lpuart_set_termios()
2018 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
2021 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
2022 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
2024 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
2029 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
2031 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
2032 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2033 termios->c_cflag |= PARENB; in lpuart_set_termios()
2035 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
2036 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2038 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2044 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
2046 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2056 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
2062 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
2065 if (old && sport->lpuart_dma_rx_use) in lpuart_set_termios()
2066 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
2068 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_set_termios()
2070 sport->port.read_status_mask = 0; in lpuart_set_termios()
2071 if (termios->c_iflag & INPCK) in lpuart_set_termios()
2072 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
2073 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
2074 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2077 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
2078 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2079 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
2080 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
2081 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2086 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2087 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
2090 /* update the per-port timeout */ in lpuart_set_termios()
2091 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
2094 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
2098 sport->port.membase + UARTCR2); in lpuart_set_termios()
2100 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
2101 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2106 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
2107 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
2108 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
2109 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
2110 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
2111 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
2114 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
2116 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
2120 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
2123 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_set_termios()
2131 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
2134 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
2135 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
2156 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
2160 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
2161 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
2180 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2189 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2205 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2206 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2207 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2219 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2221 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2222 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_set_termios()
2223 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2224 sport->is_cs7 = false; in lpuart32_set_termios()
2228 * - (7,n,1) (imx only) in lpuart32_set_termios()
2229 * - (7,e/o,1) in lpuart32_set_termios()
2230 * - (8,n,1) in lpuart32_set_termios()
2231 * - (8,m/s,1) in lpuart32_set_termios()
2232 * - (8,e/o,1) in lpuart32_set_termios()
2234 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2235 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2236 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2237 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2241 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2242 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2245 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2246 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2247 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2248 termios->c_cflag |= CS8; in lpuart32_set_termios()
2254 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2257 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2258 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2260 if (termios->c_cflag & CRTSCTS) in lpuart32_set_termios()
2265 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2271 * imx support 7-bits format, no limitation on parity when CS7 in lpuart32_set_termios()
2272 * for layerscape, parity must be enabled when CS7 to match 8-bits format in lpuart32_set_termios()
2274 if ((termios->c_cflag & CSIZE) == CS7 && !(termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2280 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2283 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2284 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2289 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2291 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2301 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2307 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2310 if (old && sport->lpuart_dma_rx_use) in lpuart32_set_termios()
2311 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2313 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_set_termios()
2315 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2316 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2317 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2318 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2319 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2322 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2323 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2324 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2325 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2326 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2331 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2332 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2335 /* update the per-port timeout */ in lpuart32_set_termios()
2336 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2339 * LPUART Transmission Complete Flag may never be set while queuing a break in lpuart32_set_termios()
2344 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2345 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2349 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2352 lpuart32_write(&sport->port, bd, UARTBAUD); in lpuart32_set_termios()
2355 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); in lpuart32_set_termios()
2357 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2358 /* re-enable the CTS if needed */ in lpuart32_set_termios()
2359 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2362 sport->is_cs7 = true; in lpuart32_set_termios()
2364 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2368 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2371 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_set_termios()
2393 port->type = PORT_LPUART; in lpuart_config_port()
2400 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2401 ret = -EINVAL; in lpuart_verify_port()
2402 if (port->irq != ser->irq) in lpuart_verify_port()
2403 ret = -EINVAL; in lpuart_verify_port()
2404 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2405 ret = -EINVAL; in lpuart_verify_port()
2406 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2407 ret = -EINVAL; in lpuart_verify_port()
2408 if (port->iobase != ser->port) in lpuart_verify_port()
2409 ret = -EINVAL; in lpuart_verify_port()
2410 if (ser->hub6 != 0) in lpuart_verify_port()
2411 ret = -EINVAL; in lpuart_verify_port()
2471 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2483 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2489 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart_console_write()
2491 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_console_write()
2494 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2497 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2499 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2502 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2504 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2507 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_console_write()
2513 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2519 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2521 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2524 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2527 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2529 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2532 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2534 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2537 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_console_write()
2551 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2558 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2573 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2575 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2579 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2589 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2600 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2607 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2622 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2635 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2652 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2653 co->index = 0; in lpuart_console_setup()
2655 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2657 return -ENODEV; in lpuart_console_setup()
2672 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2682 .index = -1,
2692 .index = -1,
2698 struct earlycon_device *dev = con->data; in lpuart_early_write()
2700 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2705 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2707 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2713 if (!device->port.membase) in lpuart_early_console_setup()
2714 return -ENODEV; in lpuart_early_console_setup()
2716 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2723 if (!device->port.membase) in lpuart32_early_console_setup()
2724 return -ENODEV; in lpuart32_early_console_setup()
2726 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2727 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2729 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2738 if (!device->port.membase) in ls1028a_early_console_setup()
2739 return -ENODEV; in ls1028a_early_console_setup()
2741 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2742 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2745 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2746 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2750 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2752 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2760 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2761 return -ENODEV; in lpuart32_imx_early_console_setup()
2763 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2764 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2765 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2769 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2770 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2771 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2772 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2773 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2774 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2775 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2776 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2801 struct uart_port *port = &sport->port; in lpuart_global_reset()
2807 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
2809 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
2820 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart_global_reset()
2823 dev_warn(sport->port.dev, in lpuart_global_reset()
2825 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2830 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; in lpuart_global_reset()
2843 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2849 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); in lpuart_probe()
2850 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2856 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2858 return -ENOMEM; in lpuart_probe()
2860 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in lpuart_probe()
2861 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2862 return PTR_ERR(sport->port.membase); in lpuart_probe()
2864 sport->port.membase += sdata->reg_off; in lpuart_probe()
2865 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2866 sport->port.dev = &pdev->dev; in lpuart_probe()
2867 sport->port.type = PORT_LPUART; in lpuart_probe()
2868 sport->devtype = sdata->devtype; in lpuart_probe()
2869 sport->rx_watermark = sdata->rx_watermark; in lpuart_probe()
2870 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || in lpuart_probe()
2875 sport->port.irq = ret; in lpuart_probe()
2876 sport->port.iotype = sdata->iotype; in lpuart_probe()
2878 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2880 sport->port.ops = &lpuart_pops; in lpuart_probe()
2881 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2882 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2885 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2887 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2888 sport->port.rs485_supported = lpuart_rs485_supported; in lpuart_probe()
2890 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2891 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2892 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2893 return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n"); in lpuart_probe()
2896 sport->baud_clk = NULL; in lpuart_probe()
2898 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2899 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2900 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2901 return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n"); in lpuart_probe()
2907 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in lpuart_probe()
2911 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2912 return -EINVAL; in lpuart_probe()
2914 sport->port.line = ret; in lpuart_probe()
2919 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2921 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2923 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2933 pm_runtime_use_autosuspend(&pdev->dev); in lpuart_probe()
2934 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); in lpuart_probe()
2935 pm_runtime_set_active(&pdev->dev); in lpuart_probe()
2936 pm_runtime_enable(&pdev->dev); in lpuart_probe()
2937 pm_runtime_mark_last_busy(&pdev->dev); in lpuart_probe()
2943 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2947 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2951 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2959 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2963 pm_runtime_disable(&pdev->dev); in lpuart_probe()
2964 pm_runtime_set_suspended(&pdev->dev); in lpuart_probe()
2965 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_probe()
2974 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2978 if (sport->dma_tx_chan) in lpuart_remove()
2979 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2981 if (sport->dma_rx_chan) in lpuart_remove()
2982 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2984 pm_runtime_disable(&pdev->dev); in lpuart_remove()
2985 pm_runtime_set_suspended(&pdev->dev); in lpuart_remove()
2986 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_remove()
3012 val = lpuart32_read(&sport->port, UARTCTRL); in serial_lpuart_enable_wakeup()
3013 baud = lpuart32_read(&sport->port, UARTBAUD); in serial_lpuart_enable_wakeup()
3016 lpuart32_write(&sport->port, 0, UARTWATER); in serial_lpuart_enable_wakeup()
3019 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); in serial_lpuart_enable_wakeup()
3025 lpuart32_write(&sport->port, val, UARTCTRL); in serial_lpuart_enable_wakeup()
3026 lpuart32_write(&sport->port, baud, UARTBAUD); in serial_lpuart_enable_wakeup()
3028 val = readb(sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3033 writeb(val, sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3039 struct tty_port *port = &sport->port.state->port; in lpuart_uport_is_active()
3046 tty_dev = tty->dev; in lpuart_uport_is_active()
3052 (!console_suspend_enabled && uart_console(&sport->port))) in lpuart_uport_is_active()
3061 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend_noirq()
3083 val = lpuart32_read(&sport->port, UARTSTAT); in lpuart_resume_noirq()
3084 lpuart32_write(&sport->port, val, UARTSTAT); in lpuart_resume_noirq()
3096 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
3099 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3102 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
3104 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
3107 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
3109 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
3111 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3113 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
3116 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
3121 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
3124 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3126 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3127 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
3130 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
3131 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
3133 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3136 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
3137 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3139 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3141 lpuart32_write(&sport->port, temp, UARTBAUD); in lpuart_suspend()
3143 temp = readb(sport->port.membase + UARTCR5); in lpuart_suspend()
3145 writeb(temp, sport->port.membase + UARTCR5); in lpuart_suspend()
3147 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3148 sport->dma_tx_in_progress = false; in lpuart_suspend()
3149 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_suspend()
3151 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_suspend()
3153 pm_runtime_disable(sport->port.dev); in lpuart_suspend()
3154 pm_runtime_set_suspended(sport->port.dev); in lpuart_suspend()
3162 struct tty_port *port = &sport->port.state->port; in lpuart_console_fixup()
3163 struct uart_port *uport = &sport->port; in lpuart_console_fixup()
3166 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers in lpuart_console_fixup()
3174 console_suspend_enabled && uart_console(&sport->port)) { in lpuart_console_fixup()
3176 mutex_lock(&port->mutex); in lpuart_console_fixup()
3178 termios.c_cflag = uport->cons->cflag; in lpuart_console_fixup()
3179 if (port->tty && termios.c_cflag == 0) in lpuart_console_fixup()
3180 termios = port->tty->termios; in lpuart_console_fixup()
3181 uport->ops->set_termios(uport, &termios, NULL); in lpuart_console_fixup()
3182 mutex_unlock(&port->mutex); in lpuart_console_fixup()
3196 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_resume()
3200 pm_runtime_set_active(sport->port.dev); in lpuart_resume()
3201 pm_runtime_enable(sport->port.dev); in lpuart_resume()
3205 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
3222 .name = "fsl-lpuart",
3251 MODULE_DESCRIPTION("Freescale lpuart serial port driver");