Lines Matching +full:data +full:- +full:ready
1 /* SPDX-License-Identifier: GPL-2.0+ */
27 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */
31 #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
32 #define ATMEL_US_DTREN BIT(16) /* Data Terminal Ready Enable */
33 #define ATMEL_US_DTRDIS BIT(17) /* Data Terminal Ready Disable */
81 #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
91 #define ATMEL_US_RXRDY BIT(0) /* Receiver Ready */
92 #define ATMEL_US_TXRDY BIT(1) /* Transmitter Ready */
99 #define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */
106 #define ATMEL_US_DSRIC BIT(17) /* Data Set Ready Input Change */
107 #define ATMEL_US_DCDIC BIT(18) /* Data Carrier Detect Input Change */
126 #define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register for USART */
127 #define ATMEL_UA_RTOR 0x28 /* Receiver Time-out Register for UART */
128 #define ATMEL_US_TO GENMASK(15, 0) /* Time-out Value */
139 #define ATMEL_US_TXRDYM(data) FIELD_PREP(GENMASK(1, 0), (data)) /* TX Ready Mode */ argument
140 #define ATMEL_US_RXRDYM(data) FIELD_PREP(GENMASK(5, 4), (data)) /* RX Ready Mode */ argument