Lines Matching +full:coexist +full:- +full:gpio +full:- +full:pin
1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
167 bool hd_start_rx; /* can start RX during half-duplex operation */
197 { .compatible = "atmel,at91rm9200-usart-serial" },
210 return __raw_readl(port->membase + reg);
215 __raw_writel(value, port->membase + reg);
220 return __raw_readb(port->membase + ATMEL_US_RHR);
225 __raw_writeb(value, port->membase + ATMEL_US_THR);
230 return ((port->rs485.flags & SER_RS485_ENABLED) &&
231 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
232 (port->iso7816.flags & SER_ISO7816_ENABLED);
237 return 100 - (desired_value * 100) / actual_value;
245 return atmel_port->use_pdc_rx;
252 return atmel_port->use_pdc_tx;
270 return atmel_port->use_dma_tx;
277 return atmel_port->use_dma_rx;
284 return atmel_port->fifo_size;
290 if (!atomic_read(&atmel_port->tasklet_shutdown))
302 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
306 if (rs485conf->flags & SER_RS485_ENABLED) {
307 dev_dbg(port->dev, "Setting UART to RS485\n");
308 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
309 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
311 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
314 rs485conf->delay_rts_after_send);
318 dev_dbg(port->dev, "Setting UART to RS232\n");
320 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
323 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
328 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
340 mck_rate = (u64)clk_get_rate(atmel_port->clk);
341 do_div(mck_rate, iso7816conf->clk);
351 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
352 fidi = (u64)iso7816conf->sc_fi;
353 do_div(fidi, iso7816conf->sc_di);
369 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
373 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
376 if (iso7816conf->tg > 255) {
377 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
379 ret = -EINVAL;
383 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
386 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
390 dev_err(port->dev, "ISO7816: Type not supported\n");
392 ret = -EINVAL;
406 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
407 } else if (fidi < atmel_port->fidi_min
408 || fidi > atmel_port->fidi_max) {
409 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
411 ret = -EINVAL;
415 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
417 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
418 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
421 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
426 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
428 dev_dbg(port->dev, "Setting UART back to RS232\n");
430 mode = atmel_port->backup_mode;
433 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
437 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
440 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
443 port->iso7816 = *iso7816conf;
449 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
461 if (atmel_port->tx_stopped)
479 if (port->rs485.flags & SER_RS485_ENABLED) {
481 port->rs485.delay_rts_after_send);
513 mctrl_gpio_set(atmel_port->gpios, mctrl);
547 return mctrl_gpio_get(atmel_port->gpios, &ret);
571 atmel_port->tx_stopped = true;
575 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
578 if (!atomic_read(&atmel_port->tasklet_shutdown))
601 /* re-enable PDC transmit */
606 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
609 /* re-enable the transmitter */
611 atmel_port->tx_stopped = false;
616 * start receiving - port is in process of being opened.
629 port->read_status_mask);
637 * Stop receiving - port is in process of being closed.
648 port->read_status_mask);
665 if (atmel_port->ms_irq_enabled)
668 atmel_port->ms_irq_enabled = true;
670 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
673 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
676 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
679 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
684 mctrl_gpio_enable_ms(atmel_port->gpios);
698 if (!atmel_port->ms_irq_enabled)
701 atmel_port->ms_irq_enabled = false;
703 mctrl_gpio_disable_ms(atmel_port->gpios);
705 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
708 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
711 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
714 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
741 struct circ_buf *ring = &atmel_port->rx_ring;
744 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
748 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
749 c->status = status;
750 c->ch = ch;
755 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
767 /* ignore side-effect */
769 port->icount.brk++;
772 port->icount.parity++;
774 port->icount.frame++;
776 port->icount.overrun++;
797 || atmel_port->break_active)) {
803 && !atmel_port->break_active) {
804 atmel_port->break_active = 1;
809 * This is either the end-of-break
813 * RXBRK will indicate start-of-break.
818 atmel_port->break_active = 0;
826 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
847 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
851 atmel_port->tx_done_mask);
854 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
861 struct uart_port *port = &atmel_port->uart;
862 struct tty_port *tport = &port->state->port;
863 struct dma_chan *chan = atmel_port->chan_tx;
870 uart_xmit_advance(port, atmel_port->tx_len);
872 spin_lock(&atmel_port->lock_tx);
873 async_tx_ack(atmel_port->desc_tx);
874 atmel_port->cookie_tx = -EINVAL;
875 atmel_port->desc_tx = NULL;
876 spin_unlock(&atmel_port->lock_tx);
878 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
886 if (!kfifo_is_empty(&tport->xmit_fifo))
887 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
890 * DMA done, re-enable TXEMPTY and signal that we can stop
893 atmel_port->hd_start_rx = true;
895 atmel_port->tx_done_mask);
904 struct dma_chan *chan = atmel_port->chan_tx;
909 dma_unmap_single(port->dev, atmel_port->tx_phys,
913 atmel_port->desc_tx = NULL;
914 atmel_port->chan_tx = NULL;
915 atmel_port->cookie_tx = -EINVAL;
924 struct tty_port *tport = &port->state->port;
925 struct dma_chan *chan = atmel_port->chan_tx;
932 if (atmel_port->desc_tx != NULL)
935 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(port)) {
945 tx_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
948 if (atmel_port->fifo_size) {
960 phys_addr = atmel_port->tx_phys + tail;
979 atmel_port->tx_len = tx_len;
988 dev_err(port->dev, "Failed to send via dma!\n");
992 dma_sync_single_for_device(port->dev, atmel_port->tx_phys,
995 atmel_port->desc_tx = desc;
996 desc->callback = atmel_complete_tx_dma;
997 desc->callback_param = atmel_port;
998 atmel_port->cookie_tx = dmaengine_submit(desc);
999 if (dma_submit_error(atmel_port->cookie_tx)) {
1000 dev_err(port->dev, "dma_submit_error %d\n",
1001 atmel_port->cookie_tx);
1008 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1015 struct tty_port *tport = &port->state->port;
1016 struct device *mfd_dev = port->dev->parent;
1027 atmel_port->chan_tx = NULL;
1030 atmel_port->chan_tx = chan;
1031 dev_info(port->dev, "using %s for tx DMA transfers\n",
1032 dma_chan_name(atmel_port->chan_tx));
1034 spin_lock_init(&atmel_port->lock_tx);
1036 BUG_ON(!PAGE_ALIGNED(tport->xmit_buf));
1037 atmel_port->tx_phys = dma_map_single(port->dev, tport->xmit_buf,
1040 if (dma_mapping_error(port->dev, atmel_port->tx_phys)) {
1041 dev_dbg(port->dev, "need to release resource of dma\n");
1044 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", __func__,
1045 UART_XMIT_SIZE, tport->xmit_buf,
1046 &atmel_port->tx_phys);
1052 config.dst_addr_width = (atmel_port->fifo_size) ?
1055 config.dst_addr = port->mapbase + ATMEL_US_THR;
1058 ret = dmaengine_slave_config(atmel_port->chan_tx,
1061 dev_err(port->dev, "DMA tx slave configuration failed\n");
1068 dev_err(port->dev, "TX channel not available, switch to pio\n");
1069 atmel_port->use_dma_tx = false;
1070 if (atmel_port->chan_tx)
1072 return -EINVAL;
1080 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1086 struct dma_chan *chan = atmel_port->chan_rx;
1091 dma_unmap_single(port->dev, atmel_port->rx_phys,
1095 atmel_port->desc_rx = NULL;
1096 atmel_port->chan_rx = NULL;
1097 atmel_port->cookie_rx = -EINVAL;
1103 struct tty_port *tport = &port->state->port;
1104 struct circ_buf *ring = &atmel_port->rx_ring;
1105 struct dma_chan *chan = atmel_port->chan_rx;
1114 atmel_port->cookie_rx,
1118 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1120 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1125 dma_sync_single_for_cpu(port->dev, atmel_port->rx_phys,
1129 * ring->head points to the end of data already written by the DMA.
1130 * ring->tail points to the beginning of data to be read by the
1135 ring->head = ATMEL_SERIAL_RX_SIZE - state.residue;
1136 BUG_ON(ring->head > ATMEL_SERIAL_RX_SIZE);
1138 * At this point ring->head may point to the first byte right after the
1140 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1142 * However ring->tail must always points inside the dma buffer:
1143 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1149 if (ring->head < ring->tail) {
1150 count = ATMEL_SERIAL_RX_SIZE - ring->tail;
1152 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1153 ring->tail = 0;
1154 port->icount.rx += count;
1158 if (ring->tail < ring->head) {
1159 count = ring->head - ring->tail;
1161 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1162 /* Wrap ring->head if needed */
1163 if (ring->head >= ATMEL_SERIAL_RX_SIZE)
1164 ring->head = 0;
1165 ring->tail = ring->head;
1166 port->icount.rx += count;
1170 dma_sync_single_for_device(port->dev, atmel_port->rx_phys,
1181 struct device *mfd_dev = port->dev->parent;
1189 ring = &atmel_port->rx_ring;
1196 atmel_port->chan_rx = NULL;
1199 atmel_port->chan_rx = chan;
1200 dev_info(port->dev, "using %s for rx DMA transfers\n",
1201 dma_chan_name(atmel_port->chan_rx));
1203 spin_lock_init(&atmel_port->lock_rx);
1205 BUG_ON(!PAGE_ALIGNED(ring->buf));
1206 atmel_port->rx_phys = dma_map_single(port->dev, ring->buf,
1210 if (dma_mapping_error(port->dev, atmel_port->rx_phys)) {
1211 dev_dbg(port->dev, "need to release resource of dma\n");
1214 dev_dbg(port->dev, "%s: mapped %zu@%p to %pad\n", __func__,
1215 ATMEL_SERIAL_RX_SIZE, ring->buf, &atmel_port->rx_phys);
1222 config.src_addr = port->mapbase + ATMEL_US_RHR;
1225 ret = dmaengine_slave_config(atmel_port->chan_rx,
1228 dev_err(port->dev, "DMA rx slave configuration failed\n");
1235 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1236 atmel_port->rx_phys,
1242 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1245 desc->callback = atmel_complete_rx_dma;
1246 desc->callback_param = port;
1247 atmel_port->desc_rx = desc;
1248 atmel_port->cookie_rx = dmaengine_submit(desc);
1249 if (dma_submit_error(atmel_port->cookie_rx)) {
1250 dev_err(port->dev, "dma_submit_error %d\n",
1251 atmel_port->cookie_rx);
1255 dma_async_issue_pending(atmel_port->chan_rx);
1260 dev_err(port->dev, "RX channel not available, switch to pio\n");
1261 atmel_port->use_dma_rx = false;
1262 if (atmel_port->chan_rx)
1264 return -EINVAL;
1271 struct uart_port *port = &atmel_port->uart;
1273 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1274 tasklet_schedule(&atmel_port->tasklet_rx);
1275 mod_timer(&atmel_port->uart_timer,
1300 &atmel_port->tasklet_rx);
1313 &atmel_port->tasklet_rx);
1327 atmel_port->break_active = 0;
1339 if (pending & atmel_port->tx_done_mask) {
1341 atmel_port->tx_done_mask);
1344 if (atmel_port->hd_start_rx) {
1347 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1349 atmel_port->hd_start_rx = false;
1353 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1369 status_change = status ^ atmel_port->irq_status_prev;
1370 atmel_port->irq_status_prev = status;
1376 port->icount.rng++;
1378 port->icount.dsr++;
1384 wake_up_interruptible(&port->state->port.delta_msr_wait);
1389 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1401 spin_lock(&atmel_port->lock_suspended);
1410 if (atmel_port->suspended) {
1411 atmel_port->pending |= pending;
1412 atmel_port->pending_status = status;
1423 spin_unlock(&atmel_port->lock_suspended);
1431 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1433 dma_unmap_single(port->dev,
1434 pdc->dma_addr,
1435 pdc->dma_size,
1445 struct tty_port *tport = &port->state->port;
1446 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1451 uart_xmit_advance(port, pdc->ofs);
1452 pdc->ofs = 0;
1454 /* more to transmit - setup next transfer */
1459 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(port)) {
1462 dma_sync_single_for_device(port->dev,
1463 pdc->dma_addr,
1464 pdc->dma_size,
1467 count = kfifo_out_linear(&tport->xmit_fifo, &tail,
1469 pdc->ofs = count;
1471 atmel_uart_writel(port, ATMEL_PDC_TPR, pdc->dma_addr + tail);
1473 /* re-enable PDC transmit */
1477 atmel_port->tx_done_mask);
1485 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1492 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1493 struct tty_port *tport = &port->state->port;
1495 pdc->buf = tport->xmit_buf;
1496 pdc->dma_addr = dma_map_single(port->dev,
1497 pdc->buf,
1500 pdc->dma_size = UART_XMIT_SIZE;
1501 pdc->ofs = 0;
1509 struct circ_buf *ring = &atmel_port->rx_ring;
1513 while (ring->head != ring->tail) {
1519 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1521 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1523 port->icount.rx++;
1534 /* ignore side-effect */
1537 port->icount.brk++;
1542 port->icount.parity++;
1544 port->icount.frame++;
1546 port->icount.overrun++;
1548 status &= port->read_status_mask;
1565 tty_flip_buffer_push(&port->state->port);
1574 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1576 dma_unmap_single(port->dev,
1577 pdc->dma_addr,
1578 pdc->dma_size,
1580 kfree(pdc->buf);
1587 struct tty_port *tport = &port->state->port;
1589 int rx_idx = atmel_port->pdc_rx_idx;
1598 pdc = &atmel_port->pdc_rx[rx_idx];
1599 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1600 tail = pdc->ofs;
1604 * is unsigned, we just need a one-way comparison to
1609 * ENDRX bit as well, so that we can safely re-enable
1612 head = min(head, pdc->dma_size);
1615 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1616 pdc->dma_size, DMA_FROM_DEVICE);
1624 count = head - tail;
1626 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1629 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1630 pdc->dma_size, DMA_FROM_DEVICE);
1632 port->icount.rx += count;
1633 pdc->ofs = head;
1640 if (head >= pdc->dma_size) {
1641 pdc->ofs = 0;
1642 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1643 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1646 atmel_port->pdc_rx_idx = rx_idx;
1648 } while (head >= pdc->dma_size);
1662 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1664 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1665 if (pdc->buf == NULL) {
1667 dma_unmap_single(port->dev,
1668 atmel_port->pdc_rx[0].dma_addr,
1671 kfree(atmel_port->pdc_rx[0].buf);
1673 atmel_port->use_pdc_rx = false;
1674 return -ENOMEM;
1676 pdc->dma_addr = dma_map_single(port->dev,
1677 pdc->buf,
1680 pdc->dma_size = PDC_BUFFER_SIZE;
1681 pdc->ofs = 0;
1684 atmel_port->pdc_rx_idx = 0;
1686 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1690 atmel_port->pdc_rx[1].dma_addr);
1703 struct uart_port *port = &atmel_port->uart;
1707 atmel_port->schedule_rx(port);
1715 struct uart_port *port = &atmel_port->uart;
1719 atmel_port->schedule_tx(port);
1726 struct device_node *np = pdev->dev.of_node;
1729 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1730 atmel_port->use_dma_rx = of_property_present(np, "dmas");
1731 atmel_port->use_pdc_rx = !atmel_port->use_dma_rx;
1733 atmel_port->use_dma_rx = false;
1734 atmel_port->use_pdc_rx = false;
1737 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1738 atmel_port->use_dma_tx = of_property_present(np, "dmas");
1739 atmel_port->use_pdc_tx = !atmel_port->use_dma_tx;
1741 atmel_port->use_dma_tx = false;
1742 atmel_port->use_pdc_tx = false;
1751 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1752 atmel_port->schedule_rx = &atmel_rx_from_dma;
1753 atmel_port->release_rx = &atmel_release_rx_dma;
1755 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1756 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1757 atmel_port->release_rx = &atmel_release_rx_pdc;
1759 atmel_port->prepare_rx = NULL;
1760 atmel_port->schedule_rx = &atmel_rx_from_ring;
1761 atmel_port->release_rx = NULL;
1765 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1766 atmel_port->schedule_tx = &atmel_tx_dma;
1767 atmel_port->release_tx = &atmel_release_tx_dma;
1769 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1770 atmel_port->schedule_tx = &atmel_tx_pdc;
1771 atmel_port->release_tx = &atmel_release_tx_pdc;
1773 atmel_port->prepare_tx = NULL;
1774 atmel_port->schedule_tx = &atmel_tx_chars;
1775 atmel_port->release_tx = NULL;
1799 atmel_port->has_frac_baudrate = false;
1800 atmel_port->has_hw_timer = false;
1801 atmel_port->is_usart = false;
1804 dev_dbg(port->dev, "Uart with hw timer");
1805 atmel_port->has_hw_timer = true;
1806 atmel_port->rtor = ATMEL_UA_RTOR;
1808 dev_dbg(port->dev, "Usart\n");
1809 atmel_port->has_frac_baudrate = true;
1810 atmel_port->has_hw_timer = true;
1811 atmel_port->is_usart = true;
1812 atmel_port->rtor = ATMEL_US_RTOR;
1818 atmel_port->fidi_min = 3;
1819 atmel_port->fidi_max = 65535;
1822 atmel_port->fidi_min = 3;
1823 atmel_port->fidi_max = 2047;
1826 atmel_port->fidi_min = 1;
1827 atmel_port->fidi_max = 2047;
1830 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1838 dev_dbg(port->dev, "This version is usart\n");
1839 atmel_port->has_frac_baudrate = true;
1840 atmel_port->has_hw_timer = true;
1841 atmel_port->is_usart = true;
1842 atmel_port->rtor = ATMEL_US_RTOR;
1846 dev_dbg(port->dev, "This version is uart\n");
1849 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1859 struct platform_device *pdev = to_platform_device(port->dev);
1868 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1869 atmel_port->ms_irq_enabled = false;
1874 retval = request_irq(port->irq, atmel_interrupt,
1876 dev_name(&pdev->dev), port);
1878 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1882 atomic_set(&atmel_port->tasklet_shutdown, 0);
1883 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1884 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1892 if (atmel_port->prepare_rx) {
1893 retval = atmel_port->prepare_rx(port);
1898 if (atmel_port->prepare_tx) {
1899 retval = atmel_port->prepare_tx(port);
1907 if (atmel_port->fifo_size) {
1921 if (atmel_port->rts_high &&
1922 atmel_port->rts_low)
1924 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1925 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1931 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1939 atmel_port->tx_stopped = false;
1941 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1945 if (!atmel_port->has_hw_timer) {
1946 mod_timer(&atmel_port->uart_timer,
1950 atmel_uart_writel(port, atmel_port->rtor,
1961 if (!atmel_port->has_hw_timer) {
1962 mod_timer(&atmel_port->uart_timer,
1966 atmel_uart_writel(port, atmel_port->rtor,
1991 atmel_port->pdc_tx.ofs = 0;
1997 atmel_port->tx_len = 0;
2011 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2014 atomic_inc(&atmel_port->tasklet_shutdown);
2020 del_timer_sync(&atmel_port->uart_timer);
2023 synchronize_irq(port->irq);
2029 tasklet_kill(&atmel_port->tasklet_rx);
2030 tasklet_kill(&atmel_port->tasklet_tx);
2042 * Shut-down the DMA.
2044 if (atmel_port->release_rx)
2045 atmel_port->release_rx(port);
2046 if (atmel_port->release_tx)
2047 atmel_port->release_tx(port);
2052 atmel_port->rx_ring.head = 0;
2053 atmel_port->rx_ring.tail = 0;
2058 free_irq(port->irq, port);
2077 clk_prepare_enable(atmel_port->clk);
2079 /* re-enable interrupts if we disabled some on suspend */
2080 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2084 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2085 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2091 clk_disable_unprepare(atmel_port->clk);
2092 if (__clk_is_enabled(atmel_port->gclk))
2093 clk_disable_unprepare(atmel_port->gclk);
2096 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2117 if (atmel_port->is_usart)
2123 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2126 switch (termios->c_cflag & CSIZE) {
2142 if (termios->c_cflag & CSTOPB)
2146 if (termios->c_cflag & PARENB) {
2148 if (termios->c_cflag & CMSPAR) {
2149 if (termios->c_cflag & PARODD)
2153 } else if (termios->c_cflag & PARODD)
2162 port->read_status_mask = ATMEL_US_OVRE;
2163 if (termios->c_iflag & INPCK)
2164 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2165 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2166 port->read_status_mask |= ATMEL_US_RXBRK;
2170 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2175 port->ignore_status_mask = 0;
2176 if (termios->c_iflag & IGNPAR)
2177 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2178 if (termios->c_iflag & IGNBRK) {
2179 port->ignore_status_mask |= ATMEL_US_RXBRK;
2184 if (termios->c_iflag & IGNPAR)
2185 port->ignore_status_mask |= ATMEL_US_OVRE;
2189 /* update the per-port timeout */
2190 uart_update_timeout(port, termios->c_cflag, baud);
2198 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2202 atmel_port->tx_stopped = true;
2205 if (port->rs485.flags & SER_RS485_ENABLED) {
2207 port->rs485.delay_rts_after_send);
2209 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2210 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2215 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2220 } else if (termios->c_cflag & CRTSCTS) {
2223 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2226 * be able to drive the RTS pin high/low when the RX
2229 * pin is high.
2230 * This mode is not activated if CTS pin is a GPIO
2232 * disabled (there must be an internal pull-up
2234 * If the RTS pin is a GPIO, the controller won't be
2255 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2261 if (atmel_port->has_frac_baudrate) {
2262 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2277 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
2290 if (!atmel_port->has_frac_baudrate) {
2291 if (__clk_is_enabled(atmel_port->gclk))
2292 clk_disable_unprepare(atmel_port->gclk);
2293 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2294 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2297 clk_set_rate(atmel_port->gclk, 16 * baud);
2298 ret = clk_prepare_enable(atmel_port->gclk);
2302 if (atmel_port->is_usart) {
2325 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2351 atmel_port->tx_stopped = false;
2356 /* CTS flow-control and modem-status interrupts */
2357 if (UART_ENABLE_MS(port, termios->c_cflag))
2367 if (termios->c_line == N_PPS) {
2368 port->flags |= UPF_HARDPPS_CD;
2373 port->flags &= ~UPF_HARDPPS_CD;
2374 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2387 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2395 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2396 int size = resource_size(mpdev->resource);
2398 release_mem_region(port->mapbase, size);
2400 if (port->flags & UPF_IOREMAP) {
2401 iounmap(port->membase);
2402 port->membase = NULL;
2411 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2413 if (port->flags & UPF_IOREMAP) {
2414 port->membase = devm_platform_ioremap_resource(mpdev, 0);
2415 if (IS_ERR(port->membase))
2416 return PTR_ERR(port->membase);
2428 port->type = PORT_ATMEL;
2439 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2440 ret = -EINVAL;
2441 if (port->irq != ser->irq)
2442 ret = -EINVAL;
2443 if (ser->io_type != SERIAL_IO_MEM)
2444 ret = -EINVAL;
2445 if (port->uartclk / 16 != ser->baud_base)
2446 ret = -EINVAL;
2447 if (port->mapbase != (unsigned long)ser->iomem_base)
2448 ret = -EINVAL;
2449 if (port->iobase != ser->port)
2450 ret = -EINVAL;
2451 if (ser->hub6 != 0)
2452 ret = -EINVAL;
2513 struct uart_port *port = &atmel_port->uart;
2514 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2519 port->iotype = UPIO_MEM;
2520 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2521 port->ops = &atmel_pops;
2522 port->fifosize = 1;
2523 port->dev = &pdev->dev;
2524 port->mapbase = mpdev->resource[0].start;
2525 port->irq = platform_get_irq(mpdev, 0);
2526 port->rs485_config = atmel_config_rs485;
2527 port->rs485_supported = atmel_rs485_supported;
2528 port->iso7816_config = atmel_config_iso7816;
2529 port->membase = NULL;
2531 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2537 port->uartclk = clk_get_rate(atmel_port->clk);
2544 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2546 port->fifosize = PDC_BUFFER_SIZE;
2547 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2549 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2568 struct uart_port *port = &atmel_ports[co->index].uart;
2578 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2586 atmel_port->tx_stopped = false;
2635 *baud = port->uartclk / (16 * quot);
2640 struct uart_port *port = &atmel_ports[co->index].uart;
2647 if (port->membase == NULL) {
2648 /* Port not initialized yet - delay setup */
2649 return -ENODEV;
2652 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2655 atmel_port->tx_stopped = false;
2673 .index = -1,
2680 struct earlycon_device *dev = con->data;
2682 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2688 if (!device->port.membase)
2689 return -ENODEV;
2691 device->con->write = atmel_serial_early_write;
2696 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2698 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2742 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2743 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2744 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2745 atmel_port->cache.rtor = atmel_uart_readl(port,
2746 atmel_port->rtor);
2747 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2748 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2749 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2753 atmel_port->may_wakeup = device_may_wakeup(dev);
2757 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2758 atmel_port->suspended = true;
2759 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2775 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2776 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2777 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2778 atmel_uart_writel(port, atmel_port->rtor,
2779 atmel_port->cache.rtor);
2780 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2782 if (atmel_port->fifo_size) {
2786 atmel_port->cache.fmr);
2788 atmel_port->cache.fimr);
2793 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2794 if (atmel_port->pending) {
2795 atmel_handle_receive(port, atmel_port->pending);
2796 atmel_handle_status(port, atmel_port->pending,
2797 atmel_port->pending_status);
2798 atmel_handle_transmit(port, atmel_port->pending);
2799 atmel_port->pending = 0;
2801 atmel_port->suspended = false;
2802 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2805 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2813 atmel_port->fifo_size = 0;
2814 atmel_port->rts_low = 0;
2815 atmel_port->rts_high = 0;
2817 if (of_property_read_u32(pdev->dev.of_node,
2818 "atmel,fifo-size",
2819 &atmel_port->fifo_size))
2822 if (!atmel_port->fifo_size)
2825 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2826 atmel_port->fifo_size = 0;
2827 dev_err(&pdev->dev, "Invalid FIFO size\n");
2839 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2840 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2841 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2842 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2844 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2845 atmel_port->fifo_size);
2846 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2847 atmel_port->rts_high);
2848 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2849 atmel_port->rts_low);
2855 struct device_node *np = pdev->dev.parent->of_node;
2860 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2863 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2864 * as compatible string. This driver is probed by at91-usart mfd driver
2866 * spi-at91-usart driver. All attributes needed by this driver are
2869 pdev->dev.of_node = np;
2873 /* port id not found in platform data nor device-tree aliases:
2874 * auto-enumerate it */
2878 ret = -ENODEV;
2884 ret = -EBUSY;
2889 atmel_port->backup_imr = 0;
2890 atmel_port->uart.line = ret;
2891 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2894 atomic_set(&atmel_port->tasklet_shutdown, 0);
2895 spin_lock_init(&atmel_port->lock_suspended);
2897 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2898 if (IS_ERR(atmel_port->clk)) {
2899 ret = PTR_ERR(atmel_port->clk);
2902 ret = clk_prepare_enable(atmel_port->clk);
2906 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2907 if (IS_ERR(atmel_port->gclk)) {
2908 ret = PTR_ERR(atmel_port->gclk);
2916 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2917 if (IS_ERR(atmel_port->gpios)) {
2918 ret = PTR_ERR(atmel_port->gpios);
2922 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2923 ret = -ENOMEM;
2927 atmel_port->rx_ring.buf = data;
2930 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2932 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2936 device_init_wakeup(&pdev->dev, 1);
2940 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2942 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2949 atmel_get_ip_name(&atmel_port->uart);
2955 clk_disable_unprepare(atmel_port->clk);
2960 kfree(atmel_port->rx_ring.buf);
2961 atmel_port->rx_ring.buf = NULL;
2963 clk_disable_unprepare(atmel_port->clk);
2964 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2983 tasklet_kill(&atmel_port->tasklet_rx);
2984 tasklet_kill(&atmel_port->tasklet_tx);
2986 device_init_wakeup(&pdev->dev, 0);
2990 kfree(atmel_port->rx_ring.buf);
2994 clear_bit(port->line, atmel_ports_in_use);
2996 pdev->dev.of_node = NULL;