1 // SPDX-License-Identifier: GPL-2.0+
17  *   - MMIO32 (regshift = 2)
18  *   - FCR is not at 2, but 3
19  *   - LCR and MCR are not at 3 and 4, they share 4
20  *   - No SCR (Instead, CHAR can be used as a scratch register)
21  *   - Divisor latch at 9, no divisor latch access bit
43 	if (!device->port.membase)  in uniphier_early_console_setup()
44 		return -ENODEV;  in uniphier_early_console_setup()
47 	device->port.iotype = UPIO_MEM32;  in uniphier_early_console_setup()
48 	device->port.regshift = UNIPHIER_UART_REGSHIFT;  in uniphier_early_console_setup()
54 	device->baud = 0;  in uniphier_early_console_setup()
58 OF_EARLYCON_DECLARE(uniphier, "socionext,uniphier-uart",
89 	 * share the same offset that must be accessed by 32-bit write/read.  in uniphier_serial_in()
92 	return (readl(p->membase + offset) >> valshift) & 0xff;  in uniphier_serial_in()
123 		writel(value, p->membase + offset);  in uniphier_serial_out()
127 		 * must be 32-bit accessed.  As this is not longer atomic safe,  in uniphier_serial_out()
130 		struct uniphier8250_priv *priv = p->private_data;  in uniphier_serial_out()
134 		spin_lock_irqsave(&priv->atomic_write_lock, flags);  in uniphier_serial_out()
135 		tmp = readl(p->membase + offset);  in uniphier_serial_out()
138 		writel(tmp, p->membase + offset);  in uniphier_serial_out()
139 		spin_unlock_irqrestore(&priv->atomic_write_lock, flags);  in uniphier_serial_out()
150 	return readl(up->port.membase + UNIPHIER_UART_DLR);  in uniphier_serial_dl_read()
155 	writel(value, up->port.membase + UNIPHIER_UART_DLR);  in uniphier_serial_dl_write()
160 	struct device *dev = &pdev->dev;  in uniphier_uart_probe()
170 		return -EINVAL;  in uniphier_uart_probe()
173 	membase = devm_ioremap(dev, regs->start, resource_size(regs));  in uniphier_uart_probe()
175 		return -ENOMEM;  in uniphier_uart_probe()
179 		return -ENOMEM;  in uniphier_uart_probe()
183 	priv->clk = devm_clk_get(dev, NULL);  in uniphier_uart_probe()
184 	if (IS_ERR(priv->clk)) {  in uniphier_uart_probe()
186 		return PTR_ERR(priv->clk);  in uniphier_uart_probe()
189 	ret = clk_prepare_enable(priv->clk);  in uniphier_uart_probe()
193 	up.port.uartclk = clk_get_rate(priv->clk);  in uniphier_uart_probe()
195 	spin_lock_init(&priv->atomic_write_lock);  in uniphier_uart_probe()
199 	up.port.mapbase = regs->start;  in uniphier_uart_probe()
214 	if (of_property_read_bool(dev->of_node, "auto-flow-control"))  in uniphier_uart_probe()
225 		clk_disable_unprepare(priv->clk);  in uniphier_uart_probe()
228 	priv->line = ret;  in uniphier_uart_probe()
239 	serial8250_unregister_port(priv->line);  in uniphier_uart_remove()
240 	clk_disable_unprepare(priv->clk);  in uniphier_uart_remove()
246 	struct uart_8250_port *up = serial8250_get_port(priv->line);  in uniphier_uart_suspend()
248 	serial8250_suspend_port(priv->line);  in uniphier_uart_suspend()
250 	if (!uart_console(&up->port) || console_suspend_enabled)  in uniphier_uart_suspend()
251 		clk_disable_unprepare(priv->clk);  in uniphier_uart_suspend()
259 	struct uart_8250_port *up = serial8250_get_port(priv->line);  in uniphier_uart_resume()
262 	if (!uart_console(&up->port) || console_suspend_enabled) {  in uniphier_uart_resume()
263 		ret = clk_prepare_enable(priv->clk);  in uniphier_uart_resume()
268 	serial8250_resume_port(priv->line);  in uniphier_uart_resume()
278 	{ .compatible = "socionext,uniphier-uart" },
287 		.name	= "uniphier-uart",
295 MODULE_DESCRIPTION("UniPhier UART driver");