Lines Matching defs:up
325 static u32 default_serial_dl_read(struct uart_8250_port *up)
328 unsigned char dll = serial_in(up, UART_DLL);
329 unsigned char dlm = serial_in(up, UART_DLM);
335 static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
337 serial_out(up, UART_DLL, value & 0xff);
338 serial_out(up, UART_DLM, value >> 8 & 0xff);
431 struct uart_8250_port *up = up_to_u8250p(p);
433 up->dl_read = default_serial_dl_read;
434 up->dl_write = default_serial_dl_write;
476 up->cur_iotype = p->iotype;
633 struct uart_8250_port *up = up_to_u8250p(port);
640 return serial8250_em485_init(up);
642 serial8250_em485_destroy(up);
714 static void serial8250_clear_IER(struct uart_8250_port *up)
716 if (up->capabilities & UART_CAP_UUE)
717 serial_out(up, UART_IER, UART_IER_UUE);
719 serial_out(up, UART_IER, 0);
727 static int __enable_rsa(struct uart_8250_port *up)
732 mode = serial_in(up, UART_RSA_MSR);
736 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
737 mode = serial_in(up, UART_RSA_MSR);
742 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
747 static void enable_rsa(struct uart_8250_port *up)
749 if (up->port.type == PORT_RSA) {
750 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
751 uart_port_lock_irq(&up->port);
752 __enable_rsa(up);
753 uart_port_unlock_irq(&up->port);
755 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
756 serial_out(up, UART_RSA_FRR, 0);
766 static void disable_rsa(struct uart_8250_port *up)
771 if (up->port.type == PORT_RSA &&
772 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
773 uart_port_lock_irq(&up->port);
775 mode = serial_in(up, UART_RSA_MSR);
779 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
780 mode = serial_in(up, UART_RSA_MSR);
785 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
786 uart_port_unlock_irq(&up->port);
795 static int size_fifo(struct uart_8250_port *up)
801 old_lcr = serial_in(up, UART_LCR);
802 serial_out(up, UART_LCR, 0);
803 old_fcr = serial_in(up, UART_FCR);
804 old_mcr = serial8250_in_MCR(up);
805 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
807 serial8250_out_MCR(up, UART_MCR_LOOP);
808 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
809 old_dl = serial_dl_read(up);
810 serial_dl_write(up, 0x0001);
811 serial_out(up, UART_LCR, UART_LCR_WLEN8);
813 serial_out(up, UART_TX, count);
815 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
817 serial_in(up, UART_RX);
818 serial_out(up, UART_FCR, old_fcr);
819 serial8250_out_MCR(up, old_mcr);
820 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
821 serial_dl_write(up, old_dl);
822 serial_out(up, UART_LCR, old_lcr);
859 static void autoconfig_has_efr(struct uart_8250_port *up)
866 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
872 * Semiconductor clone chips lock up if you try writing to the
885 up->acr = 0;
886 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
887 serial_out(up, UART_EFR, UART_EFR_ECB);
888 serial_out(up, UART_LCR, 0x00);
889 id1 = serial_icr_read(up, UART_ID1);
890 id2 = serial_icr_read(up, UART_ID2);
891 id3 = serial_icr_read(up, UART_ID3);
892 rev = serial_icr_read(up, UART_REV);
898 up->port.type = PORT_16C950;
906 up->bugs |= UART_BUG_QUOT;
918 id1 = autoconfig_read_divisor_id(up);
923 up->port.type = PORT_16850;
936 if (size_fifo(up) == 64)
937 up->port.type = PORT_16654;
939 up->port.type = PORT_16650V2;
947 static void autoconfig_8250(struct uart_8250_port *up)
951 up->port.type = PORT_8250;
953 scratch = serial_in(up, UART_SCR);
954 serial_out(up, UART_SCR, 0xa5);
955 status1 = serial_in(up, UART_SCR);
956 serial_out(up, UART_SCR, 0x5a);
957 status2 = serial_in(up, UART_SCR);
958 serial_out(up, UART_SCR, scratch);
961 up->port.type = PORT_16450;
964 static int broken_efr(struct uart_8250_port *up)
971 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
983 static void autoconfig_16550a(struct uart_8250_port *up)
989 lockdep_assert_held_once(&up->port.lock);
991 up->port.type = PORT_16550A;
992 up->capabilities |= UART_CAP_FIFO;
995 !(up->port.flags & UPF_FULL_PROBE))
1002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1003 if (serial_in(up, UART_EFR) == 0) {
1004 serial_out(up, UART_EFR, 0xA8);
1005 if (serial_in(up, UART_EFR) != 0) {
1007 up->port.type = PORT_16650;
1008 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1010 serial_out(up, UART_LCR, 0);
1011 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1013 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1014 serial_out(up, UART_FCR, 0);
1015 serial_out(up, UART_LCR, 0);
1018 up->port.type = PORT_16550A_FSL64;
1022 serial_out(up, UART_EFR, 0);
1030 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1031 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1033 autoconfig_has_efr(up);
1044 serial_out(up, UART_LCR, 0);
1045 status1 = serial8250_in_MCR(up);
1046 serial_out(up, UART_LCR, 0xE0);
1047 status2 = serial_in(up, 0x02); /* EXCR1 */
1050 serial_out(up, UART_LCR, 0);
1051 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1052 serial_out(up, UART_LCR, 0xE0);
1053 status2 = serial_in(up, 0x02); /* EXCR1 */
1054 serial_out(up, UART_LCR, 0);
1055 serial8250_out_MCR(up, status1);
1060 serial_out(up, UART_LCR, 0xE0);
1062 quot = serial_dl_read(up);
1065 if (ns16550a_goto_highspeed(up))
1066 serial_dl_write(up, quot);
1068 serial_out(up, UART_LCR, 0);
1070 up->port.uartclk = 921600*16;
1071 up->port.type = PORT_NS16550A;
1072 up->capabilities |= UART_NATSEMI;
1083 serial_out(up, UART_LCR, 0);
1084 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1085 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1088 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1089 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1090 status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1091 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1093 serial_out(up, UART_LCR, 0);
1099 up->port.type = PORT_16750;
1100 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1112 iersave = serial_in(up, UART_IER);
1113 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1114 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1119 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1120 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1126 up->port.type = PORT_XSCALE;
1127 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1137 serial_out(up, UART_IER, iersave);
1143 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1144 up->port.type = PORT_U6_16550A;
1145 up->capabilities |= UART_CAP_AFE;
1156 static void autoconfig(struct uart_8250_port *up)
1160 struct uart_port *port = &up->port;
1178 up->capabilities = 0;
1179 up->bugs = 0;
1195 scratch = serial_in(up, UART_IER);
1196 serial_out(up, UART_IER, 0);
1204 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1205 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1209 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1210 serial_out(up, UART_IER, scratch);
1222 save_mcr = serial8250_in_MCR(up);
1223 save_lcr = serial_in(up, UART_LCR);
1235 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1236 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1237 serial8250_out_MCR(up, save_mcr);
1255 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1256 serial_out(up, UART_EFR, 0);
1257 serial_out(up, UART_LCR, 0);
1259 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1261 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1263 autoconfig_8250(up);
1269 autoconfig_16550a(up);
1280 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1281 __enable_rsa(up))
1285 serial_out(up, UART_LCR, save_lcr);
1287 port->fifosize = uart_config[up->port.type].fifo_size;
1288 old_capabilities = up->capabilities;
1289 up->capabilities = uart_config[port->type].flags;
1290 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1300 serial_out(up, UART_RSA_FRR, 0);
1302 serial8250_out_MCR(up, save_mcr);
1303 serial8250_clear_fifos(up);
1304 serial_in(up, UART_RX);
1305 serial8250_clear_IER(up);
1314 fintek_8250_probe(up);
1316 if (up->capabilities != old_capabilities) {
1318 old_capabilities, up->capabilities);
1325 static void autoconfig_irq(struct uart_8250_port *up)
1327 struct uart_port *port = &up->port;
1343 save_mcr = serial8250_in_MCR(up);
1346 save_ier = serial_in(up, UART_IER);
1348 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1351 serial8250_out_MCR(up, 0);
1354 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1356 serial8250_out_MCR(up,
1361 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1363 serial_in(up, UART_LSR);
1364 serial_in(up, UART_RX);
1365 serial_in(up, UART_IIR);
1366 serial_in(up, UART_MSR);
1367 serial_out(up, UART_TX, 0xFF);
1371 serial8250_out_MCR(up, save_mcr);
1374 serial_out(up, UART_IER, save_ier);
1385 struct uart_8250_port *up = up_to_u8250p(port);
1390 serial8250_rpm_get(up);
1392 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1393 serial_port_out(port, UART_IER, up->ier);
1395 serial8250_rpm_put(up);
1522 struct uart_8250_port *up = up_to_u8250p(port);
1524 serial8250_rpm_get(up);
1525 __stop_tx(up);
1531 up->acr |= UART_ACR_TXDIS;
1532 serial_icr_write(up, UART_ACR, up->acr);
1534 serial8250_rpm_put(up);
1539 struct uart_8250_port *up = up_to_u8250p(port);
1541 if (up->dma && !up->dma->tx_dma(up))
1544 if (serial8250_set_THRI(up)) {
1545 if (up->bugs & UART_BUG_TXEN) {
1546 u16 lsr = serial_lsr_in(up);
1549 serial8250_tx_chars(up);
1556 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1557 up->acr &= ~UART_ACR_TXDIS;
1558 serial_icr_write(up, UART_ACR, up->acr);
1564 * @up: uart 8250 port
1573 void serial8250_em485_start_tx(struct uart_8250_port *up, bool toggle_ier)
1575 unsigned char mcr = serial8250_in_MCR(up);
1577 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && toggle_ier)
1578 serial8250_stop_rx(&up->port);
1580 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1584 serial8250_out_MCR(up, mcr);
1591 struct uart_8250_port *up = up_to_u8250p(port);
1592 struct uart_8250_em485 *em485 = up->em485;
1611 up->rs485_start_tx(up, true);
1613 if (up->port.rs485.delay_rts_before_send > 0) {
1616 up->port.rs485.delay_rts_before_send);
1643 struct uart_8250_port *up = up_to_u8250p(port);
1644 struct uart_8250_em485 *em485 = up->em485;
1652 serial8250_rpm_get_tx(up);
1674 struct uart_8250_port *up = up_to_u8250p(port);
1680 if (up->bugs & UART_BUG_NOMSR)
1683 mctrl_gpio_disable_ms(up->gpios);
1685 up->ier &= ~UART_IER_MSI;
1686 serial_port_out(port, UART_IER, up->ier);
1691 struct uart_8250_port *up = up_to_u8250p(port);
1697 if (up->bugs & UART_BUG_NOMSR)
1700 mctrl_gpio_enable_ms(up->gpios);
1702 up->ier |= UART_IER_MSI;
1704 serial8250_rpm_get(up);
1705 serial_port_out(port, UART_IER, up->ier);
1706 serial8250_rpm_put(up);
1709 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1711 struct uart_port *port = &up->port;
1715 ch = serial_in(up, UART_RX);
1728 lsr |= up->lsr_saved_flags;
1729 up->lsr_saved_flags = 0;
1777 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1779 struct uart_port *port = &up->port;
1783 serial8250_read_char(up, lsr);
1786 lsr = serial_in(up, UART_LSR);
1794 void serial8250_tx_chars(struct uart_8250_port *up)
1796 struct uart_port *port = &up->port;
1809 __stop_tx(up);
1813 count = up->tx_loadsz;
1820 serial_out(up, UART_TX, c);
1821 if (up->bugs & UART_BUG_TXRACE) {
1831 serial_in(up, UART_SCR);
1834 if ((up->capabilities & UART_CAP_HFIFO) &&
1835 !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1838 if ((up->capabilities & UART_CAP_MINI) &&
1839 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1852 !(up->capabilities & UART_CAP_RPM))
1853 __stop_tx(up);
1858 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1860 struct uart_port *port = &up->port;
1861 unsigned int status = serial_in(up, UART_MSR);
1863 status |= up->msr_saved_flags;
1864 up->msr_saved_flags = 0;
1865 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1883 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1898 if (!up->dma->rx_running)
1903 serial8250_rx_dma_flush(up);
1906 return up->dma->rx_dma(up);
1914 struct uart_8250_port *up = up_to_u8250p(port);
1925 status = serial_lsr_in(up);
1937 !(up->ier & (UART_IER_RLSI | UART_IER_RDI)))
1946 if (!up->dma || handle_rx_dma(up, iir))
1947 status = serial8250_rx_chars(up, status);
1949 serial8250_modem_status(up);
1950 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1951 if (!up->dma || up->dma->tx_err)
1952 serial8250_tx_chars(up);
1953 else if (!up->dma->tx_running)
1954 __stop_tx(up);
1965 struct uart_8250_port *up = up_to_u8250p(port);
1969 serial8250_rpm_get(up);
1974 serial8250_rpm_put(up);
1982 * has space available. Load it up with tx_loadsz bytes.
1989 /* TX Threshold IRQ triggered so load up FIFO */
1991 struct uart_8250_port *up = up_to_u8250p(port);
1994 serial8250_tx_chars(up);
2004 struct uart_8250_port *up = up_to_u8250p(port);
2008 serial8250_rpm_get(up);
2011 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
2015 serial8250_rpm_put(up);
2022 struct uart_8250_port *up = up_to_u8250p(port);
2026 serial8250_rpm_get(up);
2027 status = serial8250_modem_status(up);
2028 serial8250_rpm_put(up);
2031 if (up->gpios)
2032 return mctrl_gpio_get(up->gpios, &val);
2047 struct uart_8250_port *up = up_to_u8250p(port);
2052 mcr |= up->mcr;
2054 serial8250_out_MCR(up, mcr);
2071 struct uart_8250_port *up = up_to_u8250p(port);
2074 serial8250_rpm_get(up);
2077 up->lcr |= UART_LCR_SBC;
2079 up->lcr &= ~UART_LCR_SBC;
2080 serial_port_out(port, UART_LCR, up->lcr);
2082 serial8250_rpm_put(up);
2086 static bool wait_for_lsr(struct uart_8250_port *up, int bits)
2094 if (up->port.frame_time)
2095 tmout = up->port.frame_time * 2 / NSEC_PER_USEC;
2100 status = serial_lsr_in(up);
2114 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2118 wait_for_lsr(up, bits);
2120 /* Wait up to 1s for flow control if necessary */
2121 if (up->port.flags & UPF_CONS_FLOW) {
2123 unsigned int msr = serial_in(up, UART_MSR);
2124 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2141 struct uart_8250_port *up = up_to_u8250p(port);
2145 serial8250_rpm_get(up);
2156 serial8250_rpm_put(up);
2165 struct uart_8250_port *up = up_to_u8250p(port);
2175 serial8250_rpm_get(up);
2180 serial8250_clear_IER(up);
2182 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2192 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2194 serial8250_rpm_put(up);
2201 struct uart_8250_port *up = up_to_u8250p(port);
2209 if (!up->tx_loadsz)
2210 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2211 if (!up->capabilities)
2212 up->capabilities = uart_config[port->type].flags;
2213 up->mcr = 0;
2215 if (port->iotype != up->cur_iotype)
2218 serial8250_rpm_get(up);
2221 * Wake up and initialize UART
2226 up->acr = 0;
2231 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2259 * If this is an RSA port, see if we can kick it up to the
2262 enable_rsa(up);
2269 serial8250_clear_fifos(up);
2297 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2299 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2317 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2323 port->fifosize - up->tx_loadsz);
2329 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2330 up->port.irqflags |= IRQF_SHARED;
2332 retval = up->ops->setup_irq(up);
2336 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2354 wait_for_xmitr(up, UART_LSR_THRE);
2375 up->port.flags & UPF_BUG_THRE) {
2376 up->bugs |= UART_BUG_THRE;
2380 up->ops->setup_timer(up);
2388 if (up->port.flags & UPF_FOURPORT) {
2389 if (!up->port.irq)
2390 up->port.mctrl |= TIOCM_OUT1;
2396 up->port.mctrl |= TIOCM_OUT2;
2411 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2424 if (!(up->bugs & UART_BUG_TXEN)) {
2425 up->bugs |= UART_BUG_TXEN;
2429 up->bugs &= ~UART_BUG_TXEN;
2444 up->lsr_saved_flags = 0;
2445 up->msr_saved_flags = 0;
2450 if (up->dma) {
2455 else if (serial8250_request_dma(up))
2459 up->dma = NULL;
2468 up->ier = UART_IER_RLSI | UART_IER_RDI;
2481 serial8250_rpm_put(up);
2495 struct uart_8250_port *up = up_to_u8250p(port);
2498 serial8250_rpm_get(up);
2505 up->ier = 0;
2511 if (up->dma)
2512 serial8250_release_dma(up);
2530 serial8250_clear_fifos(up);
2536 disable_rsa(up);
2544 serial8250_rpm_put(up);
2546 up->ops->release_irq(up);
2560 struct uart_8250_port *up = up_to_u8250p(port);
2562 if (up->dma)
2563 serial8250_tx_dma_flush(up);
2571 struct uart_8250_port *up = up_to_u8250p(port);
2577 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2616 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2632 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2654 struct uart_8250_port *up = up_to_u8250p(port);
2657 if (is_omap1510_8250(up)) {
2669 if (up->capabilities & UART_NATSEMI)
2672 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2674 serial_dl_write(up, quot);
2759 struct uart_8250_port *up = up_to_u8250p(port);
2764 if (up->capabilities & UART_CAP_MINI) {
2770 cval = serial8250_compute_lcr(up, termios->c_cflag);
2781 serial8250_rpm_get(up);
2784 up->lcr = cval; /* Save computed LCR */
2786 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2787 if (baud < 2400 && !up->dma) {
2788 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2789 up->fcr |= UART_FCR_TRIGGER_1;
2798 if (up->capabilities & UART_CAP_AFE) {
2799 up->mcr &= ~UART_MCR_AFE;
2801 up->mcr |= UART_MCR_AFE;
2846 up->ier &= ~UART_IER_MSI;
2847 if (!(up->bugs & UART_BUG_NOMSR) &&
2848 UART_ENABLE_MS(&up->port, termios->c_cflag))
2849 up->ier |= UART_IER_MSI;
2850 if (up->capabilities & UART_CAP_UUE)
2851 up->ier |= UART_IER_UUE;
2852 if (up->capabilities & UART_CAP_RTOIE)
2853 up->ier |= UART_IER_RTOIE;
2855 serial_port_out(port, UART_IER, up->ier);
2857 if (up->capabilities & UART_CAP_EFR) {
2881 serial_port_out(port, UART_FCR, up->fcr);
2883 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2886 if (up->fcr & UART_FCR_ENABLE_FIFO)
2888 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2892 serial8250_rpm_put(up);
2969 static int serial8250_request_std_resource(struct uart_8250_port *up)
2971 unsigned int size = serial8250_port_size(up);
2972 struct uart_port *port = &up->port;
3010 static void serial8250_release_std_resource(struct uart_8250_port *up)
3012 unsigned int size = serial8250_port_size(up);
3013 struct uart_port *port = &up->port;
3042 struct uart_8250_port *up = up_to_u8250p(port);
3044 serial8250_release_std_resource(up);
3049 struct uart_8250_port *up = up_to_u8250p(port);
3051 return serial8250_request_std_resource(up);
3054 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3056 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3059 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3064 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3066 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3085 struct uart_8250_port *up = up_to_u8250p(uport);
3087 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3090 return fcr_get_rxtrig_bytes(up);
3121 struct uart_8250_port *up = up_to_u8250p(uport);
3124 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3127 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3131 serial8250_clear_fifos(up);
3132 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3133 up->fcr |= (unsigned char)rxtrig;
3134 serial_out(up, UART_FCR, up->fcr);
3181 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3183 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3186 up->port.attr_group = &serial8250_dev_attr_group;
3191 struct uart_8250_port *up = up_to_u8250p(port);
3198 ret = serial8250_request_std_resource(up);
3202 if (port->iotype != up->cur_iotype)
3206 autoconfig(up);
3210 up->bugs |= UART_BUG_NOMSR;
3213 autoconfig_irq(up);
3216 serial8250_release_std_resource(up);
3218 register_dev_spec_attr_grp(up);
3219 up->fcr = uart_config[up->port.type].fcr;
3270 void serial8250_init_port(struct uart_8250_port *up)
3272 struct uart_port *port = &up->port;
3280 up->cur_iotype = UPIO_UNKNOWN;
3284 void serial8250_set_defaults(struct uart_8250_port *up)
3286 struct uart_port *port = &up->port;
3288 if (up->port.flags & UPF_FIXED_TYPE) {
3289 unsigned int type = up->port.type;
3291 if (!up->port.fifosize)
3292 up->port.fifosize = uart_config[type].fifo_size;
3293 if (!up->tx_loadsz)
3294 up->tx_loadsz = uart_config[type].tx_loadsz;
3295 if (!up->capabilities)
3296 up->capabilities = uart_config[type].flags;
3302 if (up->dma) {
3303 if (!up->dma->tx_dma)
3304 up->dma->tx_dma = serial8250_tx_dma;
3305 if (!up->dma->rx_dma)
3306 up->dma->rx_dma = serial8250_rx_dma;
3320 struct uart_8250_port *up = up_to_u8250p(port);
3322 wait_for_xmitr(up, UART_LSR_THRE);
3329 static void serial8250_console_restore(struct uart_8250_port *up)
3331 struct uart_port *port = &up->port;
3348 serial_port_out(port, UART_LCR, up->lcr);
3349 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3352 static void fifo_wait_for_lsr(struct uart_8250_port *up, unsigned int count)
3357 if (wait_for_lsr(up, UART_LSR_THRE))
3368 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3372 unsigned int fifosize = up->tx_loadsz;
3373 struct uart_port *port = &up->port;
3380 fifo_wait_for_lsr(up, fifosize);
3398 fifo_wait_for_lsr(up, tx_count);
3408 * Thus, we assume the function is called when device is powered up.
3410 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3413 struct uart_8250_em485 *em485 = up->em485;
3414 struct uart_port *port = &up->port;
3430 serial8250_clear_IER(up);
3433 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3434 serial8250_console_restore(up);
3435 up->canary = 0;
3440 up->rs485_start_tx(up, false);
3444 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3449 !(up->capabilities & UART_CAP_MINI) &&
3453 up->tx_loadsz > 1 &&
3454 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3462 !(up->port.flags & UPF_CONS_FLOW);
3465 serial8250_console_fifo_write(up, s, count);
3473 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3478 up->rs485_stop_tx(up, false);
3490 if (up->msr_saved_flags)
3491 serial8250_modem_status(up);