Lines Matching +full:0 +full:x4038
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
99 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
100 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
104 * > 0 - number of ports
105 * = 0 - use board->num_ports
106 * < 0 - error
134 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
138 0xA000, 0x1000) },
140 0xA000, 0x1000) },
142 0xA000, 0x1000) },
144 0xA000, 0x1000) },
157 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" in moan_device()
178 unsigned int bar = 0, offset = board->first_offset; in addidata_apci7800_setup()
227 int rc = 0; in pci_hp_diva_init()
269 if (idx > 0) in pci_hp_diva_setup()
276 offset = 0x18; in pci_hp_diva_setup()
290 if (!(dev->subsystem_device & 0x1000)) in pci_inteli960ni_init()
294 pci_read_config_dword(dev, 0x44, &oldval); in pci_inteli960ni_init()
295 if (oldval == 0x00001000L) { /* RESET value */ in pci_inteli960ni_init()
299 return 0; in pci_inteli960ni_init()
313 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { in pci_plx9050_init()
314 moan_device("no memory in bar 0", dev); in pci_plx9050_init()
315 return 0; in pci_plx9050_init()
318 irq_config = 0x41; in pci_plx9050_init()
321 irq_config = 0x43; in pci_plx9050_init()
333 irq_config = 0x5b; in pci_plx9050_init()
337 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_plx9050_init()
340 writel(irq_config, p + 0x4c); in pci_plx9050_init()
345 readl(p + 0x4c); in pci_plx9050_init()
348 return 0; in pci_plx9050_init()
355 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) in pci_plx9050_exit()
361 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_plx9050_exit()
363 writel(0, p + 0x4c); in pci_plx9050_exit()
368 readl(p + 0x4c); in pci_plx9050_exit()
373 #define NI8420_INT_ENABLE_REG 0x38
374 #define NI8420_INT_ENABLE_BIT 0x2000
379 unsigned int bar = 0; in pci_ni8420_exit()
381 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8420_exit()
398 #define MITE_IOWBSR1 0xc4
399 #define MITE_IOWCR1 0xf4
400 #define MITE_LCIMR1 0x08
401 #define MITE_LCIMR2 0x10
408 unsigned int bar = 0; in pci_ni8430_exit()
410 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8430_exit()
431 bar = 0; in sbs_setup()
434 /* first four channels map to 0, 0x100, 0x200, 0x300 */ in sbs_setup()
437 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ in sbs_setup()
438 offset += idx * board->uart_offset + 0xC00; in sbs_setup()
453 #define OCT_REG_CR_OFF 0x500
459 p = pci_ioremap_bar(dev, 0); in sbs_init()
464 writeb(0x10, p + OCT_REG_CR_OFF); in sbs_init()
466 writeb(0x0, p + OCT_REG_CR_OFF); in sbs_init()
469 writeb(0x4, p + OCT_REG_CR_OFF); in sbs_init()
472 return 0; in sbs_init()
483 p = pci_ioremap_bar(dev, 0); in sbs_exit()
486 writeb(0, p + OCT_REG_CR_OFF); in sbs_exit()
508 * Note: all 10x cards have PCI device ids 0x10..
509 * all 20x cards have PCI device ids 0x20..
517 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
518 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
525 switch (dev->device & 0xfff8) { in pci_siig10x_init()
527 data = 0xffdf; in pci_siig10x_init()
530 data = 0xf7ff; in pci_siig10x_init()
533 data = 0xfffb; in pci_siig10x_init()
537 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_siig10x_init()
541 writew(readw(p + 0x28) & data, p + 0x28); in pci_siig10x_init()
542 readw(p + 0x28); in pci_siig10x_init()
544 return 0; in pci_siig10x_init()
547 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
548 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
555 pci_read_config_byte(dev, 0x6f, &data); in pci_siig20x_init()
556 pci_write_config_byte(dev, 0x6f, data & 0xef); in pci_siig20x_init()
559 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || in pci_siig20x_init()
560 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { in pci_siig20x_init()
561 pci_read_config_byte(dev, 0x73, &data); in pci_siig20x_init()
562 pci_write_config_byte(dev, 0x73, data & 0xef); in pci_siig20x_init()
564 return 0; in pci_siig20x_init()
569 unsigned int type = dev->device & 0xff00; in pci_siig_init()
571 if (type == 0x1000) in pci_siig_init()
573 if (type == 0x2000) in pci_siig_init()
584 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; in pci_siig_setup()
591 return setup_port(priv, port, bar, offset, 0); in pci_siig_setup()
600 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
604 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
605 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
606 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
607 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
608 0xD079, 0
612 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
613 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
614 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
615 0xB157, 0
619 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
620 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
643 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) in pci_timedia_probe()
645 if ((dev->subsystem_device & 0x00f0) >= 0x70) { in pci_timedia_probe()
651 return 0; in pci_timedia_probe()
659 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { in pci_timedia_init()
661 for (j = 0; ids[j]; j++) in pci_timedia_init()
665 return 0; in pci_timedia_init()
677 unsigned int bar = 0, offset = board->first_offset; in pci_timedia_setup()
680 case 0: in pci_timedia_setup()
681 bar = 0; in pci_timedia_setup()
685 bar = 0; in pci_timedia_setup()
714 case 0: in titan_400l_800l_setup()
731 return 0; in pci_xircom_init()
737 unsigned int bar = 0; in pci_ni8420_init()
739 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8420_init()
741 return 0; in pci_ni8420_init()
753 return 0; in pci_ni8420_init()
756 #define MITE_IOWBSR1_WSIZE 0xa
757 #define MITE_IOWBSR1_WIN_OFFSET 0x800
761 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
768 unsigned int bar = 0; in pci_ni8430_init()
770 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8430_init()
772 return 0; in pci_ni8430_init()
785 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) in pci_ni8430_init()
793 /* Enable IO Bus Interrupt 0 */ in pci_ni8430_init()
800 return 0; in pci_ni8430_init()
804 #define NI8430_PORTCON 0x0f
842 (priv->dev->subsystem_device & 0xff00) == 0x3000) { in pci_netmos_9900_setup()
844 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) in pci_netmos_9900_setup()
848 return setup_port(priv, port, bar, 0, board->reg_shift); in pci_netmos_9900_setup()
868 pi = c & 0xff; in pci_netmos_9900_numports()
873 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { in pci_netmos_9900_numports()
874 /* two possibilities: 0x30ps encodes number of parallel and in pci_netmos_9900_numports()
875 * serial ports, or 0x1000 indicates *something*. This is not in pci_netmos_9900_numports()
877 * to offer all functionality on functions 0..2, while still in pci_netmos_9900_numports()
880 sub_serports = dev->subsystem_device & 0xf; in pci_netmos_9900_numports()
881 if (sub_serports > 0) in pci_netmos_9900_numports()
885 return 0; in pci_netmos_9900_numports()
889 return 0; in pci_netmos_9900_numports()
894 /* subdevice 0x00PS means <P> parallel, <S> serial */ in pci_netmos_init()
895 unsigned int num_serial = dev->subsystem_device & 0xf; in pci_netmos_init()
899 return 0; in pci_netmos_init()
902 dev->subsystem_device == 0x0299) in pci_netmos_init()
903 return 0; in pci_netmos_init()
917 if (num_serial == 0) { in pci_netmos_init()
936 #define ITE_887x_MISCR 0x9c
937 #define ITE_887x_INTCBAR 0x78
938 #define ITE_887x_UARTBAR 0x7c
939 #define ITE_887x_PS0BAR 0x10
940 #define ITE_887x_POSIO0 0x60
954 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
965 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { in pci_ite887x_init()
977 if (ret != 0xff) { in pci_ite887x_init()
991 type = inb(iobase->start + 0x18) & 0x0f; in pci_ite887x_init()
994 case 0x2: /* ITE8871 (1P) */ in pci_ite887x_init()
995 case 0xa: /* ITE8875 (1P) */ in pci_ite887x_init()
996 ret = 0; in pci_ite887x_init()
998 case 0xe: /* ITE8872 (2S1P) */ in pci_ite887x_init()
1001 case 0x6: /* ITE8873 (1S) */ in pci_ite887x_init()
1004 case 0x8: /* ITE8874 (2S) */ in pci_ite887x_init()
1013 for (i = 0; i < ret; i++) { in pci_ite887x_init()
1015 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), in pci_ite887x_init()
1017 ioport &= 0x0000FF00; /* the actual base address */ in pci_ite887x_init()
1018 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), in pci_ite887x_init()
1024 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ in pci_ite887x_init()
1030 /* disable interrupts (UARTx_Routing[3:0]) */ in pci_ite887x_init()
1031 miscr &= ~(0xf << (12 - 4 * i)); in pci_ite887x_init()
1038 if (ret <= 0) { in pci_ite887x_init()
1049 /* the ioport is bit 0-15 in POSIO0R */ in pci_ite887x_exit()
1051 ioport &= 0xffff; in pci_ite887x_exit()
1059 #define PCI_VENDOR_ID_ENDRUN 0x7401
1060 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1064 /* OxSemi Tornado devices are all 0xCxxx */ in pci_oxsemi_tornado_p()
1066 (dev->device & 0xf000) != 0xc000) in pci_oxsemi_tornado_p()
1069 /* EndRun devices are all 0xExxx */ in pci_oxsemi_tornado_p()
1071 (dev->device & 0xf000) != 0xe000) in pci_oxsemi_tornado_p()
1084 unsigned int number_uarts = 0; in pci_oxsemi_tornado_init()
1087 return 0; in pci_oxsemi_tornado_init()
1089 p = pci_iomap(dev, 0, 5); in pci_oxsemi_tornado_init()
1095 if (deviceID == 0x07000200) { in pci_oxsemi_tornado_init()
1107 #define OXSEMI_TORNADO_TCR_MASK 0xf
1108 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1109 #define OXSEMI_TORNADO_CPR_MIN 0x008
1110 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1121 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1206 for (i = 0; i < ARRAY_SIZE(p); i++) { in pci_oxsemi_tornado_get_divisor()
1212 tc = p[i][0]; in pci_oxsemi_tornado_get_divisor()
1221 if (srem == 0) { in pci_oxsemi_tornado_get_divisor()
1234 quot % 2 == 0) { in pci_oxsemi_tornado_get_divisor()
1313 #define QPCR_TEST_FOR1 0x3F
1314 #define QPCR_TEST_GET1 0x00
1315 #define QPCR_TEST_FOR2 0x40
1316 #define QPCR_TEST_GET2 0x40
1317 #define QPCR_TEST_FOR3 0x80
1318 #define QPCR_TEST_GET3 0x40
1319 #define QPCR_TEST_FOR4 0xC0
1320 #define QPCR_TEST_GET4 0x80
1322 #define QOPR_CLOCK_X1 0x0000
1323 #define QOPR_CLOCK_X2 0x0001
1324 #define QOPR_CLOCK_X4 0x0002
1325 #define QOPR_CLOCK_X8 0x0003
1326 #define QOPR_CLOCK_RATE_MASK 0x0003
1332 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1334 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1341 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1342 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1343 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1344 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1345 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1346 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1347 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1349 { 0, }
1358 outb(0xBF, base + UART_LCR); in pci_quatech_rqopr()
1370 outb(0xBF, base + UART_LCR); in pci_quatech_wqopr()
1382 outb(0xBF, base + UART_LCR); in pci_quatech_rqmcr()
1384 outb(val | 0x10, base + UART_SCR); in pci_quatech_rqmcr()
1398 outb(0xBF, base + UART_LCR); in pci_quatech_wqmcr()
1400 outb(val | 0x10, base + UART_SCR); in pci_quatech_wqmcr()
1412 outb(0xBF, base + UART_LCR); in pci_quatech_has_qmcr()
1414 if (val & 0x20) { in pci_quatech_has_qmcr()
1415 outb(0x80, UART_LCR); in pci_quatech_has_qmcr()
1416 if (!(inb(UART_SCR) & 0x20)) { in pci_quatech_has_qmcr()
1421 return 0; in pci_quatech_has_qmcr()
1430 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1434 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1438 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1442 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1447 return 0; in pci_quatech_test()
1455 if (pci_quatech_test(port) < 0) in pci_quatech_clock()
1497 int rs422 = 0; in pci_quatech_rs422()
1500 return 0; in pci_quatech_rs422()
1502 pci_quatech_wqmcr(port, 0xFF); in pci_quatech_rs422()
1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); in pci_quatech_init()
1524 unsigned long base = pci_resource_start(dev, 0); in pci_quatech_init()
1528 outl(inl(base + 0x38) | 0x00002000, base + 0x38); in pci_quatech_init()
1529 tmp = inl(base + 0x3c); in pci_quatech_init()
1530 outl(tmp | 0x01000000, base + 0x3c); in pci_quatech_init()
1531 outl(tmp & ~0x01000000, base + 0x3c); in pci_quatech_init()
1534 return 0; in pci_quatech_init()
1582 ret = setup_port(priv, port, idx, 0, board->reg_shift); in ce4100_serial_setup()
1596 return setup_port(priv, port, 2, idx * 8, 0); in pci_omegapci_setup()
1611 /* RTS will control by MCR if this bit is 0 */
1624 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); in pci_fintek_rs485_config()
1642 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); in pci_fintek_rs485_config()
1644 return 0; in pci_fintek_rs485_config()
1664 config_base = 0x40 + 0x08 * idx; in pci_fintek_setup()
1669 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); in pci_fintek_setup()
1684 return 0; in pci_fintek_setup()
1704 case 0x1104: /* 4 ports */ in pci_fintek_init()
1705 case 0x1108: /* 8 ports */ in pci_fintek_init()
1706 max_port = dev->device & 0xff; in pci_fintek_init()
1708 case 0x1112: /* 12 ports */ in pci_fintek_init()
1716 bar_data[0] = pci_resource_start(dev, 5); in pci_fintek_init()
1720 for (i = 0; i < max_port; ++i) { in pci_fintek_init()
1721 /* UART0 configuration offset start from 0x40 */ in pci_fintek_init()
1722 config_base = 0x40 + 0x08 * i; in pci_fintek_init()
1725 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; in pci_fintek_init()
1728 pci_write_config_byte(dev, config_base + 0x00, 0x01); in pci_fintek_init()
1731 pci_write_config_byte(dev, config_base + 0x01, 0x33); in pci_fintek_init()
1734 pci_write_config_byte(dev, config_base + 0x04, in pci_fintek_init()
1735 (u8)(iobase & 0xff)); in pci_fintek_init()
1738 pci_write_config_byte(dev, config_base + 0x05, in pci_fintek_init()
1739 (u8)((iobase & 0xff00) >> 8)); in pci_fintek_init()
1741 pci_write_config_byte(dev, config_base + 0x06, dev->irq); in pci_fintek_init()
1747 pci_write_config_byte(dev, config_base + 0x07, 0x01); in pci_fintek_init()
1782 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; in pci_fintek_f815xxa_setup()
1785 return 0; in pci_fintek_f815xxa_setup()
1793 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) in pci_fintek_f815xxa_init()
1797 case 0x1204: /* 4 ports */ in pci_fintek_f815xxa_init()
1798 case 0x1208: /* 8 ports */ in pci_fintek_f815xxa_init()
1799 max_port = dev->device & 0xff; in pci_fintek_f815xxa_init()
1801 case 0x1212: /* 12 ports */ in pci_fintek_f815xxa_init()
1809 pci_write_config_byte(dev, 0x209, 0x40); in pci_fintek_f815xxa_init()
1811 for (i = 0; i < max_port; ++i) { in pci_fintek_f815xxa_init()
1812 /* UART0 configuration offset start from 0x2A0 */ in pci_fintek_f815xxa_init()
1813 config_base = 0x2A0 + 0x08 * i; in pci_fintek_f815xxa_init()
1816 pci_write_config_byte(dev, config_base + 0x01, 0x33); in pci_fintek_f815xxa_init()
1819 pci_write_config_byte(dev, config_base + 0, 0x01); in pci_fintek_f815xxa_init()
1856 * port registers could return 0 momentarily. Functions like in kt_serial_in()
1859 * setting IER register inadvertently to 0, if the value read in kt_serial_in()
1860 * is 0, double check with ier value in uart_8250_port and use in kt_serial_in()
1866 if (val == 0) in kt_serial_in()
1890 return 0; in pci_eg20t_init()
1934 #define CH384_XINT_ENABLE_REG 0xEB
1935 #define CH384_XINT_ENABLE_BIT 0x02
1946 case 0x3853: /* 8 ports */ in pci_wch_ch38x_init()
1953 iobase = pci_resource_start(dev, 0); in pci_wch_ch38x_init()
1968 iobase = pci_resource_start(dev, 0); in pci_wch_ch38x_exit()
1969 outb(0x0, iobase + CH384_XINT_ENABLE_REG); in pci_wch_ch38x_exit()
1985 bar = 0; in pci_sunix_setup()
1994 return setup_port(priv, port, bar, offset, 0); in pci_sunix_setup()
1997 #define MOXA_PUART_GPIO_EN 0x09
1998 #define MOXA_PUART_GPIO_OUT 0x0A
2002 #define MOXA_RS232 0x00
2003 #define MOXA_RS422 0x01
2004 #define MOXA_RS485_4W 0x0B
2005 #define MOXA_RS485_2W 0x0F
2006 #define MOXA_UIR_OFFSET 0x04
2007 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2011 MOXA_SUPP_RS232 = BIT(0),
2024 return FIELD_GET(0x00F0, device); in moxa_get_nports()
2042 switch (dev->device & 0x0F00) { in pci_moxa_supported_rs()
2043 case 0x0000: in pci_moxa_supported_rs()
2044 case 0x0600: in pci_moxa_supported_rs()
2046 case 0x0100: in pci_moxa_supported_rs()
2048 case 0x0300: in pci_moxa_supported_rs()
2051 return 0; in pci_moxa_supported_rs()
2073 return 0; in pci_moxa_set_interface()
2089 for (i = 0; i < num_ports; ++i) in pci_moxa_init()
2126 return setup_port(priv, port, bar, offset, 0); in pci_moxa_setup()
2186 .subvendor = 0xe4bf,
2588 .device = 0x4027,
2596 .device = 0x4028,
2604 .device = 0x4029,
2612 .device = 0x4019,
2620 .device = 0x4016,
2628 .device = 0x4015,
2636 .device = 0x400A,
2644 .device = 0x400E,
2652 .device = 0x400C,
2660 .device = 0x400B,
2668 .device = 0x400F,
2676 .device = 0x4010,
2684 .device = 0x4011,
2692 .device = 0x401D,
2700 .device = 0x401E,
2708 .device = 0x4013,
2716 .device = 0x4017,
2724 .device = 0x4018,
2732 .device = 0x4026,
2740 .device = 0x4021,
2748 .device = 0x8811,
2756 .device = 0x8812,
2764 .device = 0x8813,
2772 .device = 0x8814,
2779 .vendor = 0x10DB,
2780 .device = 0x8027,
2787 .vendor = 0x10DB,
2788 .device = 0x8028,
2795 .vendor = 0x10DB,
2796 .device = 0x8029,
2803 .vendor = 0x10DB,
2804 .device = 0x800C,
2811 .vendor = 0x10DB,
2812 .device = 0x800D,
2921 .vendor = 0x1c29,
2922 .device = 0x1104,
2929 .vendor = 0x1c29,
2930 .device = 0x1108,
2937 .vendor = 0x1c29,
2938 .device = 0x1112,
2956 .vendor = 0x1c29,
2957 .device = 0x1204,
2964 .vendor = 0x1c29,
2965 .device = 0x1208,
2972 .vendor = 0x1c29,
2973 .device = 0x1212,
3031 pbn_default = 0,
3182 * offset 0x10 from the UART base, while UART_IER is defined as 1
3623 .uart_offset = 0x400,
3630 .uart_offset = 0x400,
3637 .uart_offset = 0x400,
3648 .first_offset = 0x03,
3652 * This board uses the size of PCI Base region 0 to
3665 .uart_offset = 0x200,
3666 .first_offset = 0x1000,
3672 .uart_offset = 0x200,
3673 .first_offset = 0x1000,
3679 .uart_offset = 0x200,
3680 .first_offset = 0x1000,
3686 .uart_offset = 0x200,
3687 .first_offset = 0x1000,
3701 .first_offset = 0x10000,
3708 .reg_shift = 0,
3709 .first_offset = 0x20178,
3719 .uart_offset = 0x40,
3721 .first_offset = 0x200,
3727 .uart_offset = 0x40,
3729 .first_offset = 0x200,
3735 .uart_offset = 0x40,
3737 .first_offset = 0x200,
3761 .uart_offset = 0x10,
3762 .first_offset = 0x800,
3768 .uart_offset = 0x10,
3769 .first_offset = 0x800,
3775 .uart_offset = 0x10,
3776 .first_offset = 0x800,
3782 .uart_offset = 0x10,
3783 .first_offset = 0x800,
3792 .uart_offset = 0x200,
3793 .first_offset = 0x1000,
3799 .uart_offset = 0x200,
3800 .first_offset = 0x1000,
3806 .uart_offset = 0x200,
3807 .first_offset = 0x1000,
3813 .uart_offset = 0x200,
3814 .first_offset = 0x1000,
3826 .uart_offset = 0x200,
3843 .first_offset = 0x40,
3849 .first_offset = 0x40,
3855 .first_offset = 0x40,
3877 .first_offset = 0xC0,
3884 .first_offset = 0xC0,
3891 .first_offset = 0x00,
3896 .uart_offset = 0x8,
3901 .uart_offset = 0x8,
3906 .uart_offset = 0x8,
3911 .uart_offset = 0x8,
3916 .uart_offset = 0x8,
3922 .uart_offset = 0x200,
3923 .first_offset = 0x1000,
3929 .uart_offset = 0x200,
3930 .first_offset = 0x1000,
3936 .uart_offset = 0x200,
3937 .first_offset = 0x1000,
3943 .uart_offset = 0x200,
3944 .first_offset = 0x1000,
3950 .uart_offset = 0x200,
3956 .uart_offset = 0x200,
3962 .uart_offset = 0x200,
3967 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3970 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3974 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3975 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3976 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3980 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3982 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3984 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
3987 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3988 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3989 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3990 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3991 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3992 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3995 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3996 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3997 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3998 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3999 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4000 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4001 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4002 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4003 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4004 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4005 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4006 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4007 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4030 (dev->class & 0xff) > 6) in serial_pci_is_class_communication()
4033 return 0; in serial_pci_is_class_communication()
4039 * serial specs. Returns 0 on success, -ENODEV on failure.
4057 num_iomem = num_port = 0; in serial_pci_guess_board()
4058 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in serial_pci_guess_board()
4069 * If there is 1 or 0 iomem regions, and exactly one port, in serial_pci_guess_board()
4076 return 0; in serial_pci_guess_board()
4085 num_port = 0; in serial_pci_guess_board()
4086 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in serial_pci_guess_board()
4099 return 0; in serial_pci_guess_board()
4135 * <0 - error in pciserial_init_ports()
4136 * 0 - use board->num_ports in pciserial_init_ports()
4137 * >0 - number of ports in pciserial_init_ports()
4141 if (rc < 0) { in pciserial_init_ports()
4158 memset(&uart, 0, sizeof(uart)); in pciserial_init_ports()
4163 uart.port.irq = 0; in pciserial_init_ports()
4174 if (rc < 0) { in pciserial_init_ports()
4180 uart.port.irq = pci_irq_vector(dev, 0); in pciserial_init_ports()
4185 for (i = 0; i < nr_ports; i++) { in pciserial_init_ports()
4193 if (priv->line[i] < 0) { in pciserial_init_ports()
4218 for (i = 0; i < priv->nr; i++) in pciserial_detach_ports()
4240 for (i = 0; i < priv->nr; i++) in pciserial_suspend_ports()
4241 if (priv->line[i] >= 0) in pciserial_suspend_ports()
4262 for (i = 0; i < priv->nr; i++) in pciserial_resume_ports()
4263 if (priv->line[i] >= 0) in pciserial_resume_ports()
4333 if (rc == 0 && serial_pci_matches(board, &tmp)) in pciserial_init_one()
4343 return 0; in pciserial_init_one()
4361 return 0; in pciserial_suspend_one()
4380 return 0; in pciserial_resume_one()
4389 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4391 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4393 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4395 /* Advantech also use 0x3618 and 0xf618 */
4397 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4400 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4404 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4408 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4412 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4416 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4420 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4424 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4428 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4432 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4436 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4440 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4444 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4448 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4452 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4456 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4460 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4464 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4468 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4472 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 /* Unknown card - subdevice 0x1584 */
4517 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4519 /* Unknown card - subdevice 0x1588 */
4522 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4526 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4540 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4544 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4548 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4552 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4556 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4560 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4564 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4571 0x10b5, 0x106a, 0, 0,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 0, 0,
4643 0, 0,
4645 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 * For now just used the hex ID 0x950a.
4655 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4657 0, 0, pbn_b0_2_115200 },
4658 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4660 0, 0, pbn_b0_2_115200 },
4661 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4816 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4818 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4819 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4821 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4822 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4824 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4825 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4832 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4850 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4853 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4856 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015 0, 0, pbn_computone_4 },
5018 0, 0, pbn_computone_8 },
5021 0, 0, pbn_computone_6 },
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5034 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5037 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5040 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5043 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5046 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5049 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5052 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102 * ACR = 0x10, and as such are not currently fully supported.
5105 0x1204, 0x0004, 0, 0,
5108 0x1208, 0x0004, 0, 0,
5111 0x1402, 0x0002, 0, 0,
5114 0x1404, 0x0004, 0, 0,
5117 0x1208, 0x0004, 0, 0,
5121 0x1204, 0x0004, 0, 0,
5124 0x1208, 0x0004, 0, 0,
5127 0x1208, 0x0004, 0, 0,
5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 0xE4BF, PCI_ANY_ID, 0, 0,
5161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5177 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5178 0x1048, 0x1500, 0, 0,
5182 0xFF00, 0, 0, 0,
5189 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5222 0, 0,
5228 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5246 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5248 0, 0,
5253 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5255 0, 0,
5260 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5262 0, 0,
5268 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5270 0, 0,
5272 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5274 0, 0,
5276 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5278 0, 0,
5283 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5285 0, 0,
5287 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5289 0, 0,
5294 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5296 0, 0,
5301 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5303 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5305 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5307 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5312 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5314 0, 0,
5319 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5321 0, 0,
5326 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5328 0, 0,
5330 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5332 0, 0,
5334 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5336 0, 0,
5341 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5343 0, 0,
5348 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5350 0, 0,
5352 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5354 0, 0,
5356 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5358 0, 0,
5363 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5365 0, 0,
5370 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5372 0, 0,
5374 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5376 0, 0,
5381 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5383 0, 0,
5385 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5387 0, 0,
5389 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5391 0, 0,
5396 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5398 0, 0,
5400 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5402 0, 0,
5404 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5406 0, 0,
5411 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5413 0, 0,
5418 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5420 0, 0,
5422 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5424 0, 0,
5426 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5428 0, 0,
5433 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5435 0, 0,
5440 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5442 0, 0,
5444 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5446 0, 0,
5448 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5450 0, 0,
5455 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5457 0, 0,
5459 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5461 0, 0,
5463 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5465 0, 0,
5470 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5472 0, 0,
5474 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5476 0, 0,
5478 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5480 0, 0,
5485 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5487 0, 0,
5489 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5491 0, 0,
5493 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5495 0, 0,
5500 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5502 0, 0,
5504 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5506 0, 0,
5511 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5513 0, 0,
5515 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5517 0, 0,
5522 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5524 0, 0,
5526 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5528 0, 0,
5533 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5535 0, 0,
5540 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5542 0, 0,
5547 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5549 0, 0,
5554 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5556 0, 0,
5561 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5563 0, 0,
5568 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5570 0, 0,
5575 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5577 0, 0,
5582 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5584 0, 0,
5586 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5588 0, 0,
5593 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5595 0, 0,
5600 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5602 0, 0,
5604 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5606 0, 0,
5608 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5610 0, 0,
5615 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5617 0, 0,
5619 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5621 0, 0,
5626 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5628 0, 0,
5630 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5632 0, 0,
5637 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5639 0, 0,
5644 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5646 0, 0,
5654 0, 0, pbn_b2_4_921600 },
5657 0, 0, pbn_b2_8_921600 },
5667 PCI_VENDOR_ID_MAINPINE, 0x0200,
5668 0, 0, pbn_b0_2_115200 },
5671 PCI_VENDOR_ID_MAINPINE, 0x0300,
5672 0, 0, pbn_b0_4_115200 },
5675 PCI_VENDOR_ID_MAINPINE, 0x0400,
5676 0, 0, pbn_b0_2_115200 },
5679 PCI_VENDOR_ID_MAINPINE, 0x0500,
5680 0, 0, pbn_b0_4_115200 },
5683 PCI_VENDOR_ID_MAINPINE, 0x0600,
5684 0, 0, pbn_b0_2_115200 },
5687 PCI_VENDOR_ID_MAINPINE, 0x0700,
5688 0, 0, pbn_b0_4_115200 },
5691 PCI_VENDOR_ID_MAINPINE, 0x0800,
5692 0, 0, pbn_b0_8_115200 },
5695 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5696 0, 0, pbn_b0_2_115200 },
5699 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5700 0, 0, pbn_b0_4_115200 },
5703 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5704 0, 0, pbn_b0_8_115200 },
5707 PCI_VENDOR_ID_MAINPINE, 0x2000,
5708 0, 0, pbn_b0_1_115200 },
5711 PCI_VENDOR_ID_MAINPINE, 0x2100,
5712 0, 0, pbn_b0_1_115200 },
5715 PCI_VENDOR_ID_MAINPINE, 0x2200,
5716 0, 0, pbn_b0_2_115200 },
5719 PCI_VENDOR_ID_MAINPINE, 0x2300,
5720 0, 0, pbn_b0_2_115200 },
5723 PCI_VENDOR_ID_MAINPINE, 0x2400,
5724 0, 0, pbn_b0_4_115200 },
5727 PCI_VENDOR_ID_MAINPINE, 0x2500,
5728 0, 0, pbn_b0_4_115200 },
5731 PCI_VENDOR_ID_MAINPINE, 0x2600,
5732 0, 0, pbn_b0_8_115200 },
5735 PCI_VENDOR_ID_MAINPINE, 0x2700,
5736 0, 0, pbn_b0_8_115200 },
5739 PCI_VENDOR_ID_MAINPINE, 0x3000,
5740 0, 0, pbn_b0_1_115200 },
5743 PCI_VENDOR_ID_MAINPINE, 0x3100,
5744 0, 0, pbn_b0_1_115200 },
5747 PCI_VENDOR_ID_MAINPINE, 0x3200,
5748 0, 0, pbn_b0_2_115200 },
5751 PCI_VENDOR_ID_MAINPINE, 0x3300,
5752 0, 0, pbn_b0_2_115200 },
5755 PCI_VENDOR_ID_MAINPINE, 0x3400,
5756 0, 0, pbn_b0_4_115200 },
5759 PCI_VENDOR_ID_MAINPINE, 0x3500,
5760 0, 0, pbn_b0_4_115200 },
5763 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5764 0, 0, pbn_b0_8_115200 },
5767 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5768 0, 0, pbn_b0_8_115200 },
5774 { PCI_VENDOR_ID_PASEMI, 0xa004,
5775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5883 0,
5884 0,
5891 0,
5892 0,
5899 0,
5900 0,
5907 0,
5908 0,
5915 0,
5916 0,
5923 0,
5924 0,
5931 0,
5932 0,
5939 0,
5940 0,
5947 0,
5948 0,
5955 0,
5956 0,
5963 0,
5964 0,
5971 0,
5972 0,
5979 0,
5980 0,
5987 0,
5988 0,
5995 0,
5996 0,
6000 PCI_VENDOR_ID_IBM, 0x0299,
6001 0, 0, pbn_b0_bt_2_115200 },
6010 0xA000, 0x1000,
6011 0, 0, pbn_b0_1_115200 },
6015 0xA000, 0x1000,
6016 0, 0, pbn_b0_1_115200 },
6019 0xA000, 0x1000,
6020 0, 0, pbn_b0_1_115200 },
6023 0xA000, 0x1000,
6024 0, 0, pbn_b0_1_115200 },
6027 0xA000, 0x1000,
6028 0, 0, pbn_b0_1_115200 },
6031 0xA000, 0x3002,
6032 0, 0, pbn_NETMOS9900_2s_115200 },
6039 0xA000, 0x1000,
6040 0, 0, pbn_b0_1_115200 },
6043 0xA000, 0x3002,
6044 0, 0, pbn_b0_bt_2_115200 },
6047 0xA000, 0x3004,
6048 0, 0, pbn_b0_bt_4_115200 },
6054 0xA000, 0x1000,
6055 0, 0, pbn_b0_1_115200 },
6059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6081 0, 0, pbn_b0_bt_2_115200 },
6089 0, 0, pbn_b0_bt_4_115200 },
6093 0, 0, pbn_b0_bt_2_115200 },
6097 0, 0, pbn_b0_bt_4_115200 },
6101 0, 0, pbn_wch382_2 },
6105 0, 0, pbn_wch384_4 },
6109 0, 0, pbn_wch384_8 },
6113 { PCI_VENDOR_ID_REALTEK, 0x816a,
6115 0, 0, pbn_b0_1_115200 },
6117 { PCI_VENDOR_ID_REALTEK, 0x816b,
6119 0, 0, pbn_b0_1_115200 },
6122 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6123 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6124 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6125 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6126 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6127 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6130 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6131 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6134 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6143 0xffff00, pbn_default },
6147 0xffff00, pbn_default },
6151 0xffff00, pbn_default },
6152 { 0, }