Lines Matching +full:am335x +full:- +full:timer +full:- +full:1 +full:ms
1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
28 #include <linux/dma-mapping.h>
36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
38 #define OMAP_DMA_TX_KICK (1 << 2)
41 * The same errata is applicable to AM335x and DRA7x processors too.
43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
73 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
89 #define TX_TRIGGER 1
169 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
179 struct omap8250_priv *priv = up->port.private_data;
184 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
191 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
192 priv->efr |= UART_EFR_RTS;
194 priv->efr &= ~UART_EFR_RTS;
195 serial_out(up, UART_EFR, priv->efr);
204 err = pm_runtime_resume_and_get(port->dev);
210 pm_runtime_mark_last_busy(port->dev);
211 pm_runtime_put_autosuspend(port->dev);
226 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
228 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
235 unsigned int uartclk = port->uartclk;
242 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
243 priv->quot = port->custom_divisor & UART_DIV_MAX;
249 if (port->custom_divisor & (1 << 16))
250 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
252 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
259 div_13 = 1;
261 div_16 = 1;
263 abs_d13 = abs(baud - uartclk / 13 / div_13);
264 abs_d16 = abs(baud - uartclk / 16 / div_16);
267 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
268 priv->quot = div_16;
270 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
271 priv->quot = div_13;
281 if (old_scr == priv->scr)
289 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
291 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
292 serial_out(up, UART_OMAP_SCR, priv->scr);
298 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
301 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
306 struct omap8250_priv *priv = up->port.private_data;
307 struct uart_8250_dma *dma = up->dma;
311 lockdep_assert_held_once(&up->port.lock);
313 if (dma && dma->tx_running) {
316 * we have a TX-DMA operation in progress then it has been
320 priv->delayed_restore = 1;
329 serial_out(up, UART_FCR, up->fcr);
338 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
339 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
346 serial_out(up, UART_IER, up->ier);
349 serial_dl_write(up, priv->quot);
351 serial_out(up, UART_EFR, priv->efr);
355 serial_out(up, UART_XON1, priv->xon);
356 serial_out(up, UART_XOFF1, priv->xoff);
358 serial_out(up, UART_LCR, up->lcr);
362 __omap8250_set_mctrl(&up->port, up->port.mctrl);
364 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
366 if (up->port.rs485.flags & SER_RS485_ENABLED &&
367 up->port.rs485_config == serial8250_em485_config)
380 struct omap8250_priv *priv = up->port.private_data;
384 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
386 if (termios->c_cflag & CSTOPB)
388 if (termios->c_cflag & PARENB)
390 if (!(termios->c_cflag & PARODD))
392 if (termios->c_cflag & CMSPAR)
399 port->uartclk / 16 / UART_DIV_MAX,
400 port->uartclk / 13);
407 pm_runtime_get_sync(port->dev);
411 * Update the per-port timeout.
413 uart_update_timeout(port, termios->c_cflag, baud);
421 up->port.read_status_mask = UART_LSR_OE | UART_LSR_DR;
422 if (termios->c_iflag & INPCK)
423 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
424 if (termios->c_iflag & (IGNBRK | PARMRK))
425 up->port.read_status_mask |= UART_LSR_BI;
430 up->port.ignore_status_mask = 0;
431 if (termios->c_iflag & IGNPAR)
432 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
433 if (termios->c_iflag & IGNBRK) {
434 up->port.ignore_status_mask |= UART_LSR_BI;
439 if (termios->c_iflag & IGNPAR)
440 up->port.ignore_status_mask |= UART_LSR_OE;
446 if ((termios->c_cflag & CREAD) == 0)
447 up->port.ignore_status_mask |= UART_LSR_DR;
452 up->ier &= ~UART_IER_MSI;
453 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
454 up->ier |= UART_IER_MSI;
456 up->lcr = cval;
462 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
463 * - less than RX_TRIGGER number of bytes will also cause an interrupt
465 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
466 * empty - the trigger level is ignored here.
469 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
472 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
476 up->fcr = UART_FCR_ENABLE_FIFO;
477 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
478 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
480 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
483 if (up->dma)
484 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
487 priv->xon = termios->c_cc[VSTART];
488 priv->xoff = termios->c_cc[VSTOP];
490 priv->efr = 0;
491 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
493 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
494 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
495 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
497 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
498 priv->efr |= UART_EFR_CTS;
499 } else if (up->port.flags & UPF_SOFT_FLOW) {
510 if (termios->c_iflag & IXOFF) {
511 up->port.status |= UPSTAT_AUTOXOFF;
512 priv->efr |= OMAP_UART_SW_TX;
517 uart_port_unlock_irq(&up->port);
518 pm_runtime_mark_last_busy(port->dev);
519 pm_runtime_put_autosuspend(port->dev);
522 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
523 priv->latency = priv->calc_latency;
525 schedule_work(&priv->qos_work);
539 pm_runtime_get_sync(port->dev);
556 pm_runtime_mark_last_busy(port->dev);
557 pm_runtime_put_autosuspend(port->dev);
583 case 1:
591 dev_warn(up->port.dev,
602 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
605 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
609 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
622 priv->habit &= ~UART_HAS_RHR_IT_DIS;
630 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
640 struct uart_8250_port *up = serial8250_get_port(priv->line);
641 struct uart_port *port = &up->port;
645 pm_runtime_get_noresume(port->dev);
647 /* Shallow idle state wake-up to an IO interrupt? */
648 if (atomic_add_unless(&priv->active, 1, 1)) {
649 priv->latency = priv->calc_latency;
650 schedule_work(&priv->qos_work);
654 if (up->dma) {
656 pm_runtime_mark_last_busy(port->dev);
657 pm_runtime_put(port->dev);
672 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
690 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
695 up->ier = serial_port_in(port, UART_IER);
696 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
697 port->ops->stop_rx(port);
699 /* Keep restarting the timer until
702 cancel_delayed_work(&up->overrun_backoff);
706 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
707 schedule_delayed_work(&up->overrun_backoff, delay);
710 pm_runtime_mark_last_busy(port->dev);
711 pm_runtime_put(port->dev);
719 struct omap8250_priv *priv = port->private_data;
720 struct uart_8250_dma *dma = &priv->omap8250_dma;
723 if (priv->wakeirq) {
724 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
729 pm_runtime_get_sync(port->dev);
735 up->lsr_saved_flags = 0;
736 up->msr_saved_flags = 0;
739 if (dma->fn && !uart_console(port)) {
740 up->dma = &priv->omap8250_dma;
743 dev_warn_ratelimited(port->dev,
745 up->dma = NULL;
748 up->dma = NULL;
753 up->ier = UART_IER_RLSI | UART_IER_RDI;
754 serial_out(up, UART_IER, up->ier);
758 up->capabilities |= UART_CAP_RPM;
762 priv->wer = OMAP_UART_WER_MOD_WKUP;
763 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
764 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
765 serial_out(up, UART_OMAP_WER, priv->wer);
767 if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
769 up->dma->rx_dma(up);
773 enable_irq(up->port.irq);
775 pm_runtime_mark_last_busy(port->dev);
776 pm_runtime_put_autosuspend(port->dev);
783 struct omap8250_priv *priv = port->private_data;
785 pm_runtime_get_sync(port->dev);
787 flush_work(&priv->qos_work);
788 if (up->dma)
792 if (priv->habit & UART_HAS_EFR2)
797 up->ier = 0;
800 disable_irq_nosync(up->port.irq);
801 dev_pm_clear_wake_irq(port->dev);
804 up->dma = NULL;
809 if (up->lcr & UART_LCR_SBC)
810 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
813 pm_runtime_mark_last_busy(port->dev);
814 pm_runtime_put_autosuspend(port->dev);
819 struct omap8250_priv *priv = port->private_data;
822 pm_runtime_get_sync(port->dev);
825 port->ops->stop_rx(port);
826 priv->throttled = true;
829 pm_runtime_mark_last_busy(port->dev);
830 pm_runtime_put_autosuspend(port->dev);
835 struct omap8250_priv *priv = port->private_data;
839 pm_runtime_get_sync(port->dev);
843 priv->throttled = false;
844 if (up->dma)
845 up->dma->rx_dma(up);
846 up->ier |= UART_IER_RLSI | UART_IER_RDI;
847 serial_out(up, UART_IER, up->ier);
850 pm_runtime_mark_last_busy(port->dev);
851 pm_runtime_put_autosuspend(port->dev);
858 struct omap8250_priv *priv = port->private_data;
869 * Additionally there appears to be a 1 bit clock delay between writing
873 if (priv->quot) {
874 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE)
875 baud = port->uartclk / (16 * priv->quot);
877 baud = port->uartclk / (13 * priv->quot);
880 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud;
889 if (!(priv->habit & UART_HAS_NATIVE_RS485) ||
890 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
891 rs485->delay_rts_after_send > fixed_delay_rts_after_send ||
892 rs485->delay_rts_before_send > fixed_delay_rts_before_send) {
893 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
894 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
896 port->rs485_config = serial8250_em485_config;
900 rs485->delay_rts_after_send = fixed_delay_rts_after_send;
901 rs485->delay_rts_before_send = fixed_delay_rts_before_send;
903 if (rs485->flags & SER_RS485_ENABLED)
904 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN;
906 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
912 if (rs485->flags & SER_RS485_RTS_ON_SEND)
913 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL;
915 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL;
917 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
925 /* Must be called while priv->rx_dma_lock is held */
928 struct uart_8250_dma *dma = p->dma;
929 struct tty_port *tty_port = &p->port.state->port;
930 struct omap8250_priv *priv = p->port.private_data;
931 struct dma_chan *rxchan = dma->rxchan;
938 if (!dma->rx_running)
941 cookie = dma->rx_cookie;
942 dma->rx_running = 0;
944 /* Re-enable RX FIFO interrupt now that transfer is complete */
945 if (priv->habit & UART_HAS_RHR_IT_DIS) {
953 count = dma->rx_size - state.residue + state.in_flight_bytes;
954 if (count < dma->rx_size) {
965 poll_count--)
968 if (poll_count == -1)
969 dev_err(p->port.dev, "teardown incomplete\n");
974 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
976 p->port.icount.rx += ret;
977 p->port.icount.buf_overrun += count - ret;
986 struct omap8250_priv *priv = p->port.private_data;
987 struct uart_8250_dma *dma = p->dma;
992 uart_port_lock_irqsave(&p->port, &flags);
999 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
1001 uart_port_unlock_irqrestore(&p->port, flags);
1005 if (!priv->throttled) {
1006 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1007 serial_out(p, UART_IER, p->ier);
1008 if (!(priv->habit & UART_HAS_EFR2))
1012 uart_port_unlock_irqrestore(&p->port, flags);
1017 struct omap8250_priv *priv = p->port.private_data;
1018 struct uart_8250_dma *dma = p->dma;
1023 spin_lock_irqsave(&priv->rx_dma_lock, flags);
1025 if (!dma->rx_running) {
1026 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1030 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
1032 ret = dmaengine_pause(dma->rxchan);
1034 priv->rx_dma_broken = true;
1037 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1042 struct omap8250_priv *priv = p->port.private_data;
1043 struct uart_8250_dma *dma = p->dma;
1050 lockdep_assert_held_once(&p->port.lock);
1052 if (priv->rx_dma_broken)
1053 return -EINVAL;
1055 spin_lock_irqsave(&priv->rx_dma_lock, flags);
1057 if (dma->rx_running) {
1060 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
1066 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1067 serial_out(p, UART_IER, p->ier);
1072 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
1073 dma->rx_size, DMA_DEV_TO_MEM,
1076 err = -EBUSY;
1080 dma->rx_running = 1;
1081 desc->callback = __dma_rx_complete;
1082 desc->callback_param = p;
1084 dma->rx_cookie = dmaengine_submit(desc);
1091 if (priv->habit & UART_HAS_RHR_IT_DIS) {
1097 dma_async_issue_pending(dma->rxchan);
1099 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1108 struct uart_8250_dma *dma = p->dma;
1109 struct tty_port *tport = &p->port.state->port;
1112 struct omap8250_priv *priv = p->port.private_data;
1114 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
1117 uart_port_lock_irqsave(&p->port, &flags);
1119 dma->tx_running = 0;
1121 uart_xmit_advance(&p->port, dma->tx_size);
1123 if (priv->delayed_restore) {
1124 priv->delayed_restore = 0;
1128 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1129 uart_write_wakeup(&p->port);
1131 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) {
1137 } else if (p->capabilities & UART_CAP_RPM) {
1142 dma->tx_err = 1;
1146 uart_port_unlock_irqrestore(&p->port, flags);
1151 struct uart_8250_dma *dma = p->dma;
1152 struct omap8250_priv *priv = p->port.private_data;
1153 struct tty_port *tport = &p->port.state->port;
1156 int skip_byte = -1;
1159 if (dma->tx_running)
1161 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) {
1168 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1169 ret = -EBUSY;
1176 sg_init_table(&sg, 1);
1177 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1,
1178 UART_XMIT_SIZE, dma->tx_addr);
1179 if (ret != 1) {
1184 dma->tx_size = sg_dma_len(&sg);
1186 if (priv->habit & OMAP_DMA_TX_KICK) {
1206 if (tx_lvl == p->tx_loadsz) {
1207 ret = -EBUSY;
1210 if (dma->tx_size < 4) {
1211 ret = -EINVAL;
1214 if (!kfifo_get(&tport->xmit_fifo, &c)) {
1215 ret = -EINVAL;
1220 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1,
1221 UART_XMIT_SIZE, dma->tx_addr);
1224 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV,
1227 ret = -EBUSY;
1231 dma->tx_running = 1;
1233 desc->callback = omap_8250_dma_tx_complete;
1234 desc->callback_param = p;
1236 dma->tx_cookie = dmaengine_submit(desc);
1238 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1241 dma_async_issue_pending(dma->txchan);
1242 if (dma->tx_err)
1243 dma->tx_err = 0;
1249 dma->tx_err = 1;
1285 lockdep_assert_held_once(&up->port.lock);
1291 (up->ier & UART_IER_RDI)) {
1298 * periodic timeouts, re-enable interrupts.
1300 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1301 serial_out(up, UART_IER, up->ier);
1305 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1306 serial_out(up, UART_IER, up->ier);
1313 * use the default routine in the non-DMA case and this one for with DMA.
1318 struct omap8250_priv *priv = up->port.private_data;
1332 if (priv->habit & UART_HAS_EFR2)
1339 if (status & UART_LSR_THRE && up->dma->tx_err) {
1340 if (uart_tx_stopped(&up->port) ||
1341 kfifo_is_empty(&up->port.state->port.xmit_fifo)) {
1342 up->dma->tx_err = 0;
1356 return 1;
1368 return -EINVAL;
1375 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1381 .rx_trigger = 1,
1408 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1409 { .compatible = "ti,omap2-uart" },
1410 { .compatible = "ti,omap3-uart" },
1411 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1412 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1413 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1414 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1421 struct device_node *np = pdev->dev.of_node;
1431 dev_err(&pdev->dev, "missing registers\n");
1432 return -EINVAL;
1435 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1437 return -ENOMEM;
1439 membase = devm_ioremap(&pdev->dev, regs->start,
1442 return -ENODEV;
1445 up.port.dev = &pdev->dev;
1446 up.port.mapbase = regs->start;
1495 clk = devm_clk_get(&pdev->dev, NULL);
1497 if (PTR_ERR(clk) == -EPROBE_DEFER)
1498 return -EPROBE_DEFER;
1504 if (of_property_read_u32(np, "overrun-throttle-ms",
1508 pdata = of_device_get_match_data(&pdev->dev);
1510 priv->habit |= pdata->habit;
1514 dev_warn(&pdev->dev,
1519 priv->membase = membase;
1520 priv->line = -ENODEV;
1521 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1522 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1523 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1524 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1526 spin_lock_init(&priv->rx_dma_lock);
1530 device_set_wakeup_capable(&pdev->dev, true);
1531 if (of_property_read_bool(np, "wakeup-source"))
1532 device_set_wakeup_enable(&pdev->dev, true);
1534 pm_runtime_enable(&pdev->dev);
1535 pm_runtime_use_autosuspend(&pdev->dev);
1540 * prevent an unsafe default policy with lossy characters on wake-up.
1544 if (!of_get_available_child_count(pdev->dev.of_node))
1545 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1547 pm_runtime_get_sync(&pdev->dev);
1551 priv->rx_trigger = RX_TRIGGER;
1552 priv->tx_trigger = TX_TRIGGER;
1562 ret = of_property_count_strings(np, "dma-names");
1565 struct uart_8250_dma *dma = &priv->omap8250_dma;
1567 dma->fn = the_no_dma_filter_fn;
1568 dma->tx_dma = omap_8250_tx_dma;
1569 dma->rx_dma = omap_8250_rx_dma;
1571 dma_params = pdata->dma_params;
1574 dma->rx_size = dma_params->rx_size;
1575 dma->rxconf.src_maxburst = dma_params->rx_trigger;
1576 dma->txconf.dst_maxburst = dma_params->tx_trigger;
1577 priv->rx_trigger = dma_params->rx_trigger;
1578 priv->tx_trigger = dma_params->tx_trigger;
1580 dma->rx_size = RX_TRIGGER;
1581 dma->rxconf.src_maxburst = RX_TRIGGER;
1582 dma->txconf.dst_maxburst = TX_TRIGGER;
1588 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0,
1589 dev_name(&pdev->dev), priv);
1593 priv->wakeirq = irq_of_parse_and_map(np, 1);
1597 dev_err(&pdev->dev, "unable to register 8250 port\n");
1600 priv->line = ret;
1601 pm_runtime_mark_last_busy(&pdev->dev);
1602 pm_runtime_put_autosuspend(&pdev->dev);
1605 pm_runtime_dont_use_autosuspend(&pdev->dev);
1606 pm_runtime_put_sync(&pdev->dev);
1607 flush_work(&priv->qos_work);
1608 pm_runtime_disable(&pdev->dev);
1609 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1619 err = pm_runtime_resume_and_get(&pdev->dev);
1621 dev_err(&pdev->dev, "Failed to resume hardware\n");
1623 up = serial8250_get_port(priv->line);
1624 omap_8250_shutdown(&up->port);
1625 serial8250_unregister_port(priv->line);
1626 priv->line = -ENODEV;
1627 pm_runtime_dont_use_autosuspend(&pdev->dev);
1628 pm_runtime_put_sync(&pdev->dev);
1629 flush_work(&priv->qos_work);
1630 pm_runtime_disable(&pdev->dev);
1631 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1632 device_set_wakeup_capable(&pdev->dev, false);
1641 priv->is_suspending = true;
1651 priv->is_suspending = false;
1657 struct uart_8250_port *up = serial8250_get_port(priv->line);
1660 serial8250_suspend_port(priv->line);
1666 priv->wer = 0;
1667 serial_out(up, UART_OMAP_WER, priv->wer);
1668 if (uart_console(&up->port) && console_suspend_enabled)
1670 flush_work(&priv->qos_work);
1678 struct uart_8250_port *up = serial8250_get_port(priv->line);
1681 if (uart_console(&up->port) && console_suspend_enabled) {
1687 serial8250_resume_port(priv->line);
1702 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1706 return 1;
1712 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
1726 * module clkctrl status bits will be 1 instead of 3 blocking idle
1742 /* By experiments, 1us enough for reset complete on AM335x */
1744 udelay(1);
1746 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1750 return -ETIMEDOUT;
1761 if (priv->line >= 0)
1762 up = serial8250_get_port(priv->line);
1764 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1775 serial_out(up, UART_OMAP_WER, priv->wer);
1779 if (up && up->dma && up->dma->rxchan)
1782 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1783 schedule_work(&priv->qos_work);
1784 atomic_set(&priv->active, 0);
1795 if (atomic_read(&priv->active))
1798 if (priv->line >= 0)
1799 up = serial8250_get_port(priv->line);
1802 uart_port_lock_irq(&up->port);
1804 uart_port_unlock_irq(&up->port);
1807 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
1808 uart_port_lock_irq(&up->port);
1810 uart_port_unlock_irq(&up->port);
1813 atomic_set(&priv->active, 1);
1814 priv->latency = priv->calc_latency;
1815 schedule_work(&priv->qos_work);
1838 idx = *omap_str - '0';