Lines Matching defs:up
178 struct uart_8250_port *up = up_to_u8250p(port);
179 struct omap8250_priv *priv = up->port.private_data;
184 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
189 lcr = serial_in(up, UART_LCR);
190 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
195 serial_out(up, UART_EFR, priv->efr);
196 serial_out(up, UART_LCR, lcr);
223 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
226 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
228 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
275 static void omap8250_update_scr(struct uart_8250_port *up,
280 old_scr = serial_in(up, UART_OMAP_SCR);
290 serial_out(up, UART_OMAP_SCR,
292 serial_out(up, UART_OMAP_SCR, priv->scr);
295 static void omap8250_update_mdr1(struct uart_8250_port *up,
299 omap_8250_mdr1_errataset(up, priv);
301 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
304 static void omap8250_restore_regs(struct uart_8250_port *up)
306 struct omap8250_priv *priv = up->port.private_data;
307 struct uart_8250_dma *dma = up->dma;
308 u8 mcr = serial8250_in_MCR(up);
311 lockdep_assert_held_once(&up->port.lock);
324 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
325 serial_out(up, UART_EFR, UART_EFR_ECB);
327 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
328 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
329 serial_out(up, UART_FCR, up->fcr);
331 omap8250_update_scr(up, priv);
333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
335 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
337 serial_out(up, UART_TI752_TLR,
341 serial_out(up, UART_LCR, 0);
344 serial8250_out_MCR(up, mcr);
346 serial_out(up, UART_IER, up->ier);
348 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
349 serial_dl_write(up, priv->quot);
351 serial_out(up, UART_EFR, priv->efr);
354 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
355 serial_out(up, UART_XON1, priv->xon);
356 serial_out(up, UART_XOFF1, priv->xoff);
358 serial_out(up, UART_LCR, up->lcr);
360 omap8250_update_mdr1(up, priv);
362 __omap8250_set_mctrl(&up->port, up->port.mctrl);
364 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
366 if (up->port.rs485.flags & SER_RS485_ENABLED &&
367 up->port.rs485_config == serial8250_em485_config)
368 serial8250_em485_stop_tx(up, true);
379 struct uart_8250_port *up = up_to_u8250p(port);
380 struct omap8250_priv *priv = up->port.private_data;
421 up->port.read_status_mask = UART_LSR_OE | UART_LSR_DR;
423 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
425 up->port.read_status_mask |= UART_LSR_BI;
430 up->port.ignore_status_mask = 0;
432 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
434 up->port.ignore_status_mask |= UART_LSR_BI;
440 up->port.ignore_status_mask |= UART_LSR_OE;
447 up->port.ignore_status_mask |= UART_LSR_DR;
452 up->ier &= ~UART_IER_MSI;
453 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
454 up->ier |= UART_IER_MSI;
456 up->lcr = cval;
476 up->fcr = UART_FCR_ENABLE_FIFO;
477 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
478 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
483 if (up->dma)
491 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
493 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
494 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
495 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
497 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
499 } else if (up->port.flags & UPF_SOFT_FLOW) {
511 up->port.status |= UPSTAT_AUTOXOFF;
515 omap8250_restore_regs(up);
517 uart_port_unlock_irq(&up->port);
536 struct uart_8250_port *up = up_to_u8250p(port);
544 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
545 efr = serial_in(up, UART_EFR);
546 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
547 serial_out(up, UART_LCR, 0);
549 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
550 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
551 serial_out(up, UART_EFR, efr);
552 serial_out(up, UART_LCR, 0);
560 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
591 dev_warn(up->port.dev,
640 struct uart_8250_port *up = serial8250_get_port(priv->line);
641 struct uart_port *port = &up->port;
647 /* Shallow idle state wake-up to an IO interrupt? */
654 if (up->dma) {
677 efr2 = serial_in(up, UART_OMAP_EFR2);
678 timeout_h = serial_in(up, UART_OMAP_TO_H);
679 timeout_l = serial_in(up, UART_OMAP_TO_L);
680 serial_out(up, UART_OMAP_TO_H, 0xFF);
681 serial_out(up, UART_OMAP_TO_L, 0xFF);
682 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
683 serial_in(up, UART_IIR);
684 serial_out(up, UART_OMAP_EFR2, efr2);
685 serial_out(up, UART_OMAP_TO_H, timeout_h);
686 serial_out(up, UART_OMAP_TO_L, timeout_l);
690 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
695 up->ier = port->serial_in(port, UART_IER);
696 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
702 cancel_delayed_work(&up->overrun_backoff);
706 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
707 schedule_delayed_work(&up->overrun_backoff, delay);
718 struct uart_8250_port *up = up_to_u8250p(port);
731 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
733 serial_out(up, UART_LCR, UART_LCR_WLEN8);
735 up->lsr_saved_flags = 0;
736 up->msr_saved_flags = 0;
740 up->dma = &priv->omap8250_dma;
741 ret = serial8250_request_dma(up);
745 up->dma = NULL;
748 up->dma = NULL;
753 up->ier = UART_IER_RLSI | UART_IER_RDI;
754 serial_out(up, UART_IER, up->ier);
758 up->capabilities |= UART_CAP_RPM;
761 /* Enable module level wake up */
765 serial_out(up, UART_OMAP_WER, priv->wer);
767 if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
769 up->dma->rx_dma(up);
773 enable_irq(up->port.irq);
782 struct uart_8250_port *up = up_to_u8250p(port);
788 if (up->dma)
789 omap_8250_rx_dma_flush(up);
791 serial_out(up, UART_OMAP_WER, 0);
793 serial_out(up, UART_OMAP_EFR2, 0x0);
797 up->ier = 0;
798 serial_out(up, UART_IER, 0);
800 disable_irq_nosync(up->port.irq);
803 serial8250_release_dma(up);
804 up->dma = NULL;
809 if (up->lcr & UART_LCR_SBC)
810 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
811 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
836 struct uart_8250_port *up = up_to_u8250p(port);
844 if (up->dma)
845 up->dma->rx_dma(up);
846 up->ier |= UART_IER_RLSI | UART_IER_RDI;
847 serial_out(up, UART_IER, up->ier);
859 struct uart_8250_port *up = up_to_u8250p(port);
890 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
894 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
917 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
1256 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1262 omap_8250_rx_dma_flush(up);
1265 return omap_8250_rx_dma(up);
1268 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1272 if (handle_rx_dma(up, iir)) {
1273 status = serial8250_rx_chars(up, status);
1274 omap_8250_rx_dma(up);
1281 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1285 lockdep_assert_held_once(&up->port.lock);
1291 (up->ier & UART_IER_RDI)) {
1292 omap_8250_rx_dma(up);
1293 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1300 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1301 serial_out(up, UART_IER, up->ier);
1302 omap_8250_rx_dma_flush(up);
1303 serial_in(up, UART_IIR);
1304 serial_out(up, UART_OMAP_EFR2, 0x0);
1305 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1306 serial_out(up, UART_IER, up->ier);
1317 struct uart_8250_port *up = up_to_u8250p(port);
1318 struct omap8250_priv *priv = up->port.private_data;
1333 am654_8250_handle_rx_dma(up, iir, status);
1335 status = omap_8250_handle_rx_dma(up, iir, status);
1338 serial8250_modem_status(up);
1339 if (status & UART_LSR_THRE && up->dma->tx_err) {
1340 if (uart_tx_stopped(&up->port) ||
1341 kfifo_is_empty(&up->port.state->port.xmit_fifo)) {
1342 up->dma->tx_err = 0;
1343 serial8250_tx_chars(up);
1349 if (omap_8250_tx_dma(up))
1350 serial8250_tx_chars(up);
1424 struct uart_8250_port up;
1444 memset(&up, 0, sizeof(up));
1445 up.port.dev = &pdev->dev;
1446 up.port.mapbase = regs->start;
1447 up.port.membase = membase;
1456 up.port.type = PORT_8250;
1457 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW;
1458 up.port.private_data = priv;
1460 up.tx_loadsz = 64;
1461 up.capabilities = UART_CAP_FIFO;
1469 up.capabilities |= UART_CAP_RPM;
1471 up.port.set_termios = omap_8250_set_termios;
1472 up.port.set_mctrl = omap8250_set_mctrl;
1473 up.port.pm = omap_8250_pm;
1474 up.port.startup = omap_8250_startup;
1475 up.port.shutdown = omap_8250_shutdown;
1476 up.port.throttle = omap_8250_throttle;
1477 up.port.unthrottle = omap_8250_unthrottle;
1478 up.port.rs485_config = omap8250_rs485_config;
1480 up.port.rs485_supported = serial8250_em485_supported;
1481 up.rs485_start_tx = serial8250_em485_start_tx;
1482 up.rs485_stop_tx = serial8250_em485_stop_tx;
1483 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1485 ret = uart_read_port_properties(&up.port);
1489 up.port.regshift = OMAP_UART_REGSHIFT;
1490 up.port.fifosize = 64;
1492 if (!up.port.uartclk) {
1500 up.port.uartclk = clk_get_rate(clk);
1505 &up.overrun_backoff_time_ms) != 0)
1506 up.overrun_backoff_time_ms = 0;
1512 if (!up.port.uartclk) {
1513 up.port.uartclk = DEFAULT_CLK_SPEED;
1540 * prevent an unsafe default policy with lossy characters on wake-up.
1549 omap_serial_fill_features_erratas(&up, priv);
1550 up.port.handle_irq = omap8250_no_handle_irq;
1587 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN);
1588 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0,
1595 ret = serial8250_register_8250_port(&up);
1616 struct uart_8250_port *up;
1623 up = serial8250_get_port(priv->line);
1624 omap_8250_shutdown(&up->port);
1657 struct uart_8250_port *up = serial8250_get_port(priv->line);
1667 serial_out(up, UART_OMAP_WER, priv->wer);
1668 if (uart_console(&up->port) && console_suspend_enabled)
1678 struct uart_8250_port *up = serial8250_get_port(priv->line);
1681 if (uart_console(&up->port) && console_suspend_enabled) {
1695 static int omap8250_lost_context(struct uart_8250_port *up)
1699 val = serial_in(up, UART_OMAP_SCR);
1759 struct uart_8250_port *up = NULL;
1762 up = serial8250_get_port(priv->line);
1771 if (up) {
1773 omap8250_update_mdr1(up, priv);
1775 serial_out(up, UART_OMAP_WER, priv->wer);
1779 if (up && up->dma && up->dma->rxchan)
1780 omap_8250_rx_dma_flush(up);
1792 struct uart_8250_port *up = NULL;
1799 up = serial8250_get_port(priv->line);
1801 if (up && omap8250_lost_context(up)) {
1802 uart_port_lock_irq(&up->port);
1803 omap8250_restore_regs(up);
1804 uart_port_unlock_irq(&up->port);
1807 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
1808 uart_port_lock_irq(&up->port);
1809 omap_8250_rx_dma(up);
1810 uart_port_unlock_irq(&up->port);