Lines Matching +full:ri +full:- +full:override
1 // SPDX-License-Identifier: GPL-2.0+
99 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
101 /* Override any modem control signals if needed */ in dw8250_modify_msr()
103 value |= d->msr_mask_on; in dw8250_modify_msr()
104 value &= ~d->msr_mask_off; in dw8250_modify_msr()
134 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
150 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_check_lcr()
151 void __iomem *addr = p->membase + (offset << p->regshift); in dw8250_check_lcr()
154 if (offset != UART_LCR || d->uart_16550_compatible) in dw8250_check_lcr()
158 while (tries--) { in dw8250_check_lcr()
167 if (p->type == PORT_OCTEON) in dw8250_check_lcr()
171 if (p->iotype == UPIO_MEM32) in dw8250_check_lcr()
173 else if (p->iotype == UPIO_MEM32BE) in dw8250_check_lcr()
179 * FIXME: this deadlocks if port->lock is already held in dw8250_check_lcr()
180 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); in dw8250_check_lcr()
189 unsigned int delay_threshold = tries - 1000; in dw8250_tx_wait_empty()
192 while (tries--) { in dw8250_tx_wait_empty()
193 lsr = readb (p->membase + (UART_LSR << p->regshift)); in dw8250_tx_wait_empty()
194 up->lsr_saved_flags |= lsr & up->lsr_save_mask; in dw8250_tx_wait_empty()
201 * the buffer has still not emptied, allow more time for low- in dw8250_tx_wait_empty()
210 writeb(value, p->membase + (offset << p->regshift)); in dw8250_serial_out()
225 u32 value = readb(p->membase + (offset << p->regshift)); in dw8250_serial_in()
233 u8 value = __raw_readq(p->membase + (offset << p->regshift)); in dw8250_serial_inq()
241 __raw_writeq(value, p->membase + (offset << p->regshift)); in dw8250_serial_outq()
243 __raw_readq(p->membase + (UART_LCR << p->regshift)); in dw8250_serial_outq()
251 writel(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32()
257 u32 value = readl(p->membase + (offset << p->regshift)); in dw8250_serial_in32()
264 iowrite32be(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32be()
270 u32 value = ioread32be(p->membase + (offset << p->regshift)); in dw8250_serial_in32be()
279 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_handle_irq()
282 unsigned int quirks = d->pdata->quirks; in dw8250_handle_irq()
287 * There are ways to get Designware-based UARTs into a state where in dw8250_handle_irq()
294 * so we limit the workaround only to non-DMA mode. in dw8250_handle_irq()
296 if (!up->dma && rx_timeout) { in dw8250_handle_irq()
307 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { in dw8250_handle_irq()
323 serial_port_in(p, d->pdata->usr_reg); in dw8250_handle_irq()
337 rate = clk_get_rate(d->clk); in dw8250_clk_work_cb()
341 up = serial8250_get_port(d->data.line); in dw8250_clk_work_cb()
343 serial8250_update_uartclk(&up->port, rate); in dw8250_clk_work_cb()
356 * the clk and tty-port mutexes lock. It happens if clock rate change in dw8250_clk_notifier_cb()
358 * tty-port mutex lock and clk_set_rate() function invocation and in dw8250_clk_notifier_cb()
359 * vise-versa. Anyway if we didn't have the reference clock alteration in dw8250_clk_notifier_cb()
364 queue_work(system_unbound_wq, &d->clk_work); in dw8250_clk_notifier_cb()
375 pm_runtime_get_sync(port->dev); in dw8250_do_pm()
380 pm_runtime_put_sync_suspend(port->dev); in dw8250_do_pm()
387 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_set_termios()
391 clk_disable_unprepare(d->clk); in dw8250_set_termios()
392 rate = clk_round_rate(d->clk, newrate); in dw8250_set_termios()
395 * Note that any clock-notifier worker will block in in dw8250_set_termios()
398 ret = clk_set_rate(d->clk, newrate); in dw8250_set_termios()
400 p->uartclk = rate; in dw8250_set_termios()
402 clk_prepare_enable(d->clk); in dw8250_set_termios()
412 if (up->capabilities & UART_CAP_IRDA) { in dw8250_set_ldisc()
413 if (termios->c_line == N_IRDA) in dw8250_set_ldisc()
438 return param == chan->device->dev; in dw8250_idma_filter()
443 /* Platforms with iDMA 64-bit */ in dw8250_setup_dma_filter()
444 if (platform_get_resource_byname(to_platform_device(p->dev), IORESOURCE_MEM, "lpss_priv")) { in dw8250_setup_dma_filter()
445 data->data.dma.rx_param = p->dev->parent; in dw8250_setup_dma_filter()
446 data->data.dma.tx_param = p->dev->parent; in dw8250_setup_dma_filter()
447 data->data.dma.fn = dw8250_idma_filter; in dw8250_setup_dma_filter()
449 data->data.dma.fn = dw8250_fallback_dma_filter; in dw8250_setup_dma_filter()
465 struct uart_port *up = &p->port; in dw8250_prepare_tx_dma()
466 struct uart_8250_dma *dma = p->dma; in dw8250_prepare_tx_dma()
470 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | in dw8250_prepare_tx_dma()
471 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | in dw8250_prepare_tx_dma()
478 struct uart_port *up = &p->port; in dw8250_prepare_rx_dma()
479 struct uart_8250_dma *dma = p->dma; in dw8250_prepare_rx_dma()
483 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | in dw8250_prepare_rx_dma()
484 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | in dw8250_prepare_rx_dma()
491 unsigned int quirks = data->pdata->quirks; in dw8250_quirks()
492 u32 cpr_value = data->pdata->cpr_value; in dw8250_quirks()
495 data->data.cpr_value = cpr_value; in dw8250_quirks()
499 p->serial_in = dw8250_serial_inq; in dw8250_quirks()
500 p->serial_out = dw8250_serial_outq; in dw8250_quirks()
501 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; in dw8250_quirks()
502 p->type = PORT_OCTEON; in dw8250_quirks()
503 data->skip_autocfg = true; in dw8250_quirks()
508 p->serial_out = dw8250_serial_out38x; in dw8250_quirks()
510 p->set_termios = dw8250_do_set_termios; in dw8250_quirks()
512 data->data.dma.txconf.device_fc = 1; in dw8250_quirks()
513 data->data.dma.rxconf.device_fc = 1; in dw8250_quirks()
514 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; in dw8250_quirks()
515 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; in dw8250_quirks()
518 p->iotype = UPIO_MEM32; in dw8250_quirks()
519 p->regshift = 2; in dw8250_quirks()
520 p->serial_in = dw8250_serial_in32; in dw8250_quirks()
521 data->uart_16550_compatible = true; in dw8250_quirks()
533 struct uart_port *p = &up->port; in dw8250_probe()
534 struct device *dev = &pdev->dev; in dw8250_probe()
541 return dev_err_probe(dev, -EINVAL, "no registers defined\n"); in dw8250_probe()
543 spin_lock_init(&p->lock); in dw8250_probe()
544 p->pm = dw8250_do_pm; in dw8250_probe()
545 p->type = PORT_8250; in dw8250_probe()
546 p->flags = UPF_FIXED_PORT; in dw8250_probe()
547 p->dev = dev; in dw8250_probe()
548 p->set_ldisc = dw8250_set_ldisc; in dw8250_probe()
549 p->set_termios = dw8250_set_termios; in dw8250_probe()
553 return -ENOMEM; in dw8250_probe()
555 p->private_data = &data->data; in dw8250_probe()
557 p->mapbase = regs->start; in dw8250_probe()
558 p->mapsize = resource_size(regs); in dw8250_probe()
560 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize); in dw8250_probe()
561 if (!p->membase) in dw8250_probe()
562 return -ENOMEM; in dw8250_probe()
565 /* no interrupt -> fall back to polling */ in dw8250_probe()
566 if (err == -ENXIO) in dw8250_probe()
571 switch (p->iotype) { in dw8250_probe()
573 p->serial_in = dw8250_serial_in; in dw8250_probe()
574 p->serial_out = dw8250_serial_out; in dw8250_probe()
577 p->serial_in = dw8250_serial_in32; in dw8250_probe()
578 p->serial_out = dw8250_serial_out32; in dw8250_probe()
581 p->serial_in = dw8250_serial_in32be; in dw8250_probe()
582 p->serial_out = dw8250_serial_out32be; in dw8250_probe()
585 return -ENODEV; in dw8250_probe()
588 if (device_property_read_bool(dev, "dcd-override")) { in dw8250_probe()
590 data->msr_mask_on |= UART_MSR_DCD; in dw8250_probe()
591 data->msr_mask_off |= UART_MSR_DDCD; in dw8250_probe()
594 if (device_property_read_bool(dev, "dsr-override")) { in dw8250_probe()
596 data->msr_mask_on |= UART_MSR_DSR; in dw8250_probe()
597 data->msr_mask_off |= UART_MSR_DDSR; in dw8250_probe()
600 if (device_property_read_bool(dev, "cts-override")) { in dw8250_probe()
602 data->msr_mask_on |= UART_MSR_CTS; in dw8250_probe()
603 data->msr_mask_off |= UART_MSR_DCTS; in dw8250_probe()
606 if (device_property_read_bool(dev, "ri-override")) { in dw8250_probe()
608 data->msr_mask_off |= UART_MSR_RI; in dw8250_probe()
609 data->msr_mask_off |= UART_MSR_TERI; in dw8250_probe()
613 data->clk = devm_clk_get_optional_enabled(dev, "baudclk"); in dw8250_probe()
614 if (data->clk == NULL) in dw8250_probe()
615 data->clk = devm_clk_get_optional_enabled(dev, NULL); in dw8250_probe()
616 if (IS_ERR(data->clk)) in dw8250_probe()
617 return dev_err_probe(dev, PTR_ERR(data->clk), in dw8250_probe()
620 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); in dw8250_probe()
621 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; in dw8250_probe()
623 if (data->clk) in dw8250_probe()
624 p->uartclk = clk_get_rate(data->clk); in dw8250_probe()
627 if (!p->uartclk) in dw8250_probe()
628 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n"); in dw8250_probe()
630 data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk"); in dw8250_probe()
631 if (IS_ERR(data->pclk)) in dw8250_probe()
632 return PTR_ERR(data->pclk); in dw8250_probe()
634 data->rst = devm_reset_control_array_get_optional_exclusive(dev); in dw8250_probe()
635 if (IS_ERR(data->rst)) in dw8250_probe()
636 return PTR_ERR(data->rst); in dw8250_probe()
638 reset_control_deassert(data->rst); in dw8250_probe()
640 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst); in dw8250_probe()
644 data->uart_16550_compatible = device_property_read_bool(dev, "snps,uart-16550-compatible"); in dw8250_probe()
646 data->pdata = device_get_match_data(p->dev); in dw8250_probe()
647 if (data->pdata) in dw8250_probe()
651 if (data->uart_16550_compatible) in dw8250_probe()
652 p->handle_irq = NULL; in dw8250_probe()
653 else if (data->pdata) in dw8250_probe()
654 p->handle_irq = dw8250_handle_irq; in dw8250_probe()
658 if (!data->skip_autocfg) in dw8250_probe()
662 if (p->fifosize) { in dw8250_probe()
663 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; in dw8250_probe()
664 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; in dw8250_probe()
665 up->dma = &data->data.dma; in dw8250_probe()
668 data->data.line = serial8250_register_8250_port(up); in dw8250_probe()
669 if (data->data.line < 0) in dw8250_probe()
670 return data->data.line; in dw8250_probe()
677 if (data->clk) { in dw8250_probe()
678 err = clk_notifier_register(data->clk, &data->clk_notifier); in dw8250_probe()
681 queue_work(system_unbound_wq, &data->clk_work); in dw8250_probe()
695 struct device *dev = &pdev->dev; in dw8250_remove()
699 if (data->clk) { in dw8250_remove()
700 clk_notifier_unregister(data->clk, &data->clk_notifier); in dw8250_remove()
702 flush_work(&data->clk_work); in dw8250_remove()
705 serial8250_unregister_port(data->data.line); in dw8250_remove()
715 serial8250_suspend_port(data->data.line); in dw8250_suspend()
724 serial8250_resume_port(data->data.line); in dw8250_resume()
733 clk_disable_unprepare(data->clk); in dw8250_runtime_suspend()
735 clk_disable_unprepare(data->pclk); in dw8250_runtime_suspend()
744 clk_prepare_enable(data->pclk); in dw8250_runtime_resume()
746 clk_prepare_enable(data->clk); in dw8250_runtime_resume()
782 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
783 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
784 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
785 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
786 { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
787 { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
817 .name = "dw-apb-uart",
831 MODULE_ALIAS("platform:dw-apb-uart");