Lines Matching refs:sw
39 struct tb_switch *sw;
43 sw = kunit_kzalloc(test, sizeof(*sw), GFP_KERNEL);
44 if (!sw)
47 sw->config.upstream_port_number = upstream_port;
48 sw->config.depth = tb_route_length(route);
49 sw->config.route_hi = upper_32_bits(route);
50 sw->config.route_lo = lower_32_bits(route);
51 sw->config.enabled = 0;
52 sw->config.max_port_number = max_port_number;
54 size = (sw->config.max_port_number + 1) * sizeof(*sw->ports);
55 sw->ports = kunit_kzalloc(test, size, GFP_KERNEL);
56 if (!sw->ports)
59 for (i = 0; i <= sw->config.max_port_number; i++) {
60 sw->ports[i].sw = sw;
61 sw->ports[i].port = i;
62 sw->ports[i].config.port_number = i;
64 kunit_ida_init(test, &sw->ports[i].in_hopids);
65 kunit_ida_init(test, &sw->ports[i].out_hopids);
69 return sw;
74 struct tb_switch *sw;
76 sw = alloc_switch(test, 0, 7, 13);
77 if (!sw)
80 sw->config.vendor_id = 0x8086;
81 sw->config.device_id = 0x9a1b;
83 sw->ports[0].config.type = TB_TYPE_PORT;
84 sw->ports[0].config.max_in_hop_id = 7;
85 sw->ports[0].config.max_out_hop_id = 7;
87 sw->ports[1].config.type = TB_TYPE_PORT;
88 sw->ports[1].config.max_in_hop_id = 19;
89 sw->ports[1].config.max_out_hop_id = 19;
90 sw->ports[1].total_credits = 60;
91 sw->ports[1].ctl_credits = 2;
92 sw->ports[1].dual_link_port = &sw->ports[2];
94 sw->ports[2].config.type = TB_TYPE_PORT;
95 sw->ports[2].config.max_in_hop_id = 19;
96 sw->ports[2].config.max_out_hop_id = 19;
97 sw->ports[2].total_credits = 60;
98 sw->ports[2].ctl_credits = 2;
99 sw->ports[2].dual_link_port = &sw->ports[1];
100 sw->ports[2].link_nr = 1;
102 sw->ports[3].config.type = TB_TYPE_PORT;
103 sw->ports[3].config.max_in_hop_id = 19;
104 sw->ports[3].config.max_out_hop_id = 19;
105 sw->ports[3].total_credits = 60;
106 sw->ports[3].ctl_credits = 2;
107 sw->ports[3].dual_link_port = &sw->ports[4];
109 sw->ports[4].config.type = TB_TYPE_PORT;
110 sw->ports[4].config.max_in_hop_id = 19;
111 sw->ports[4].config.max_out_hop_id = 19;
112 sw->ports[4].total_credits = 60;
113 sw->ports[4].ctl_credits = 2;
114 sw->ports[4].dual_link_port = &sw->ports[3];
115 sw->ports[4].link_nr = 1;
117 sw->ports[5].config.type = TB_TYPE_DP_HDMI_IN;
118 sw->ports[5].config.max_in_hop_id = 9;
119 sw->ports[5].config.max_out_hop_id = 9;
120 sw->ports[5].cap_adap = -1;
122 sw->ports[6].config.type = TB_TYPE_DP_HDMI_IN;
123 sw->ports[6].config.max_in_hop_id = 9;
124 sw->ports[6].config.max_out_hop_id = 9;
125 sw->ports[6].cap_adap = -1;
127 sw->ports[7].config.type = TB_TYPE_NHI;
128 sw->ports[7].config.max_in_hop_id = 11;
129 sw->ports[7].config.max_out_hop_id = 11;
130 sw->ports[7].config.nfc_credits = 0x41800000;
132 sw->ports[8].config.type = TB_TYPE_PCIE_DOWN;
133 sw->ports[8].config.max_in_hop_id = 8;
134 sw->ports[8].config.max_out_hop_id = 8;
136 sw->ports[9].config.type = TB_TYPE_PCIE_DOWN;
137 sw->ports[9].config.max_in_hop_id = 8;
138 sw->ports[9].config.max_out_hop_id = 8;
140 sw->ports[10].disabled = true;
141 sw->ports[11].disabled = true;
143 sw->ports[12].config.type = TB_TYPE_USB3_DOWN;
144 sw->ports[12].config.max_in_hop_id = 8;
145 sw->ports[12].config.max_out_hop_id = 8;
147 sw->ports[13].config.type = TB_TYPE_USB3_DOWN;
148 sw->ports[13].config.max_in_hop_id = 8;
149 sw->ports[13].config.max_out_hop_id = 8;
151 return sw;
156 struct tb_switch *sw;
158 sw = alloc_host(test);
159 if (!sw)
162 sw->generation = 4;
163 sw->credit_allocation = true;
164 sw->max_usb3_credits = 32;
165 sw->min_dp_aux_credits = 1;
166 sw->min_dp_main_credits = 0;
167 sw->max_pcie_credits = 64;
168 sw->max_dma_credits = 14;
170 return sw;
175 struct tb_switch *sw;
177 sw = alloc_host_usb4(test);
178 if (!sw)
181 sw->ports[10].config.type = TB_TYPE_DP_HDMI_IN;
182 sw->ports[10].config.max_in_hop_id = 9;
183 sw->ports[10].config.max_out_hop_id = 9;
184 sw->ports[10].cap_adap = -1;
185 sw->ports[10].disabled = false;
187 return sw;
195 struct tb_switch *sw;
197 sw = alloc_switch(test, route, 1, 19);
198 if (!sw)
201 sw->config.vendor_id = 0x8086;
202 sw->config.device_id = 0x15ef;
204 sw->ports[0].config.type = TB_TYPE_PORT;
205 sw->ports[0].config.max_in_hop_id = 8;
206 sw->ports[0].config.max_out_hop_id = 8;
208 sw->ports[1].config.type = TB_TYPE_PORT;
209 sw->ports[1].config.max_in_hop_id = 19;
210 sw->ports[1].config.max_out_hop_id = 19;
211 sw->ports[1].total_credits = 60;
212 sw->ports[1].ctl_credits = 2;
213 sw->ports[1].dual_link_port = &sw->ports[2];
215 sw->ports[2].config.type = TB_TYPE_PORT;
216 sw->ports[2].config.max_in_hop_id = 19;
217 sw->ports[2].config.max_out_hop_id = 19;
218 sw->ports[2].total_credits = 60;
219 sw->ports[2].ctl_credits = 2;
220 sw->ports[2].dual_link_port = &sw->ports[1];
221 sw->ports[2].link_nr = 1;
223 sw->ports[3].config.type = TB_TYPE_PORT;
224 sw->ports[3].config.max_in_hop_id = 19;
225 sw->ports[3].config.max_out_hop_id = 19;
226 sw->ports[3].total_credits = 60;
227 sw->ports[3].ctl_credits = 2;
228 sw->ports[3].dual_link_port = &sw->ports[4];
230 sw->ports[4].config.type = TB_TYPE_PORT;
231 sw->ports[4].config.max_in_hop_id = 19;
232 sw->ports[4].config.max_out_hop_id = 19;
233 sw->ports[4].total_credits = 60;
234 sw->ports[4].ctl_credits = 2;
235 sw->ports[4].dual_link_port = &sw->ports[3];
236 sw->ports[4].link_nr = 1;
238 sw->ports[5].config.type = TB_TYPE_PORT;
239 sw->ports[5].config.max_in_hop_id = 19;
240 sw->ports[5].config.max_out_hop_id = 19;
241 sw->ports[5].total_credits = 60;
242 sw->ports[5].ctl_credits = 2;
243 sw->ports[5].dual_link_port = &sw->ports[6];
245 sw->ports[6].config.type = TB_TYPE_PORT;
246 sw->ports[6].config.max_in_hop_id = 19;
247 sw->ports[6].config.max_out_hop_id = 19;
248 sw->ports[6].total_credits = 60;
249 sw->ports[6].ctl_credits = 2;
250 sw->ports[6].dual_link_port = &sw->ports[5];
251 sw->ports[6].link_nr = 1;
253 sw->ports[7].config.type = TB_TYPE_PORT;
254 sw->ports[7].config.max_in_hop_id = 19;
255 sw->ports[7].config.max_out_hop_id = 19;
256 sw->ports[7].total_credits = 60;
257 sw->ports[7].ctl_credits = 2;
258 sw->ports[7].dual_link_port = &sw->ports[8];
260 sw->ports[8].config.type = TB_TYPE_PORT;
261 sw->ports[8].config.max_in_hop_id = 19;
262 sw->ports[8].config.max_out_hop_id = 19;
263 sw->ports[8].total_credits = 60;
264 sw->ports[8].ctl_credits = 2;
265 sw->ports[8].dual_link_port = &sw->ports[7];
266 sw->ports[8].link_nr = 1;
268 sw->ports[9].config.type = TB_TYPE_PCIE_UP;
269 sw->ports[9].config.max_in_hop_id = 8;
270 sw->ports[9].config.max_out_hop_id = 8;
272 sw->ports[10].config.type = TB_TYPE_PCIE_DOWN;
273 sw->ports[10].config.max_in_hop_id = 8;
274 sw->ports[10].config.max_out_hop_id = 8;
276 sw->ports[11].config.type = TB_TYPE_PCIE_DOWN;
277 sw->ports[11].config.max_in_hop_id = 8;
278 sw->ports[11].config.max_out_hop_id = 8;
280 sw->ports[12].config.type = TB_TYPE_PCIE_DOWN;
281 sw->ports[12].config.max_in_hop_id = 8;
282 sw->ports[12].config.max_out_hop_id = 8;
284 sw->ports[13].config.type = TB_TYPE_DP_HDMI_OUT;
285 sw->ports[13].config.max_in_hop_id = 9;
286 sw->ports[13].config.max_out_hop_id = 9;
287 sw->ports[13].cap_adap = -1;
289 sw->ports[14].config.type = TB_TYPE_DP_HDMI_OUT;
290 sw->ports[14].config.max_in_hop_id = 9;
291 sw->ports[14].config.max_out_hop_id = 9;
292 sw->ports[14].cap_adap = -1;
294 sw->ports[15].disabled = true;
296 sw->ports[16].config.type = TB_TYPE_USB3_UP;
297 sw->ports[16].config.max_in_hop_id = 8;
298 sw->ports[16].config.max_out_hop_id = 8;
300 sw->ports[17].config.type = TB_TYPE_USB3_DOWN;
301 sw->ports[17].config.max_in_hop_id = 8;
302 sw->ports[17].config.max_out_hop_id = 8;
304 sw->ports[18].config.type = TB_TYPE_USB3_DOWN;
305 sw->ports[18].config.max_in_hop_id = 8;
306 sw->ports[18].config.max_out_hop_id = 8;
308 sw->ports[19].config.type = TB_TYPE_USB3_DOWN;
309 sw->ports[19].config.max_in_hop_id = 8;
310 sw->ports[19].config.max_out_hop_id = 8;
313 return sw;
316 upstream_port = tb_upstream_port(sw);
337 return sw;
344 struct tb_switch *sw;
346 sw = alloc_dev_default(test, parent, route, bonded);
347 if (!sw)
350 sw->ports[13].config.type = TB_TYPE_DP_HDMI_IN;
351 sw->ports[13].config.max_in_hop_id = 9;
352 sw->ports[13].config.max_out_hop_id = 9;
354 sw->ports[14].config.type = TB_TYPE_DP_HDMI_IN;
355 sw->ports[14].config.max_in_hop_id = 9;
356 sw->ports[14].config.max_out_hop_id = 9;
358 return sw;
365 struct tb_switch *sw;
368 sw = alloc_dev_default(test, parent, route, bonded);
369 if (!sw)
380 sw->ports[i].disabled = true;
383 sw->ports[i].disabled = true;
385 sw->ports[13].cap_adap = 0;
386 sw->ports[14].cap_adap = 0;
389 sw->ports[i].disabled = true;
391 sw->generation = 4;
392 sw->credit_allocation = true;
393 sw->max_usb3_credits = 109;
394 sw->min_dp_aux_credits = 0;
395 sw->min_dp_main_credits = 0;
396 sw->max_pcie_credits = 30;
397 sw->max_dma_credits = 1;
399 return sw;
406 struct tb_switch *sw;
408 sw = alloc_dev_default(test, parent, route, bonded);
409 if (!sw)
412 sw->generation = 4;
413 sw->credit_allocation = true;
414 sw->max_usb3_credits = 14;
415 sw->min_dp_aux_credits = 1;
416 sw->min_dp_main_credits = 18;
417 sw->max_pcie_credits = 32;
418 sw->max_dma_credits = 14;
420 return sw;
511 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
523 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
570 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
582 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
633 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
645 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
717 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
729 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
820 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
832 KUNIT_EXPECT_EQ(test, tb_route(p->sw), test_data[i].route);
916 KUNIT_EXPECT_EQ(test, tb_route(in_port->sw), test_data[i].route);
920 KUNIT_EXPECT_EQ(test, tb_route(out_port->sw), test_data[i].route);
978 KUNIT_EXPECT_EQ(test, tb_route(in_port->sw), test_data[i].route);
982 KUNIT_EXPECT_EQ(test, tb_route(out_port->sw), test_data[i].route);
1058 KUNIT_EXPECT_EQ(test, tb_route(in_port->sw), test_data[i].route);
1062 KUNIT_EXPECT_EQ(test, tb_route(out_port->sw), test_data[i].route);
1138 KUNIT_EXPECT_EQ(test, tb_route(in_port->sw), test_data[i].route);
1142 KUNIT_EXPECT_EQ(test, tb_route(out_port->sw), test_data[i].route);
1230 KUNIT_EXPECT_EQ(test, tb_route(in_port->sw), test_data[i].route);
1234 KUNIT_EXPECT_EQ(test, tb_route(out_port->sw), test_data[i].route);
1322 KUNIT_EXPECT_EQ(test, tb_route(in_port->sw), test_data[i].route);
1326 KUNIT_EXPECT_EQ(test, tb_route(out_port->sw), test_data[i].route);