Lines Matching +full:0 +full:x740
29 TB_SWITCH_CAP_TMU = 0x03,
30 TB_SWITCH_CAP_VSE = 0x05,
34 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
35 TB_VSE_CAP_TIME2 = 0x03,
36 TB_VSE_CAP_CP_LP = 0x04,
37 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
41 TB_PORT_CAP_PHY = 0x01,
42 TB_PORT_CAP_POWER = 0x02,
43 TB_PORT_CAP_TIME1 = 0x03,
44 TB_PORT_CAP_ADAP = 0x04,
45 TB_PORT_CAP_VSE = 0x05,
46 TB_PORT_CAP_USB4 = 0x06,
50 TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
65 u8 cap; /* if cap == 0x05 then we have a extended capability */
141 bool fl_cs:1; /* set to 0 before access */
145 bool not_present:1; /* should be 0 */
165 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
167 /* DWORD 0 */
185 * milliseconds. Writing 0x00 is interpreted
196 #define ROUTER_CS_1 0x01
197 #define ROUTER_CS_3 0x03
199 #define ROUTER_CS_4 0x04
201 #define ROUTER_CS_4_CMUV_V1 0x10
202 #define ROUTER_CS_4_CMUV_V2 0x20
203 #define ROUTER_CS_5 0x05
204 #define ROUTER_CS_5_SLP BIT(0)
213 #define ROUTER_CS_6 0x06
214 #define ROUTER_CS_6_SLPR BIT(0)
220 #define ROUTER_CS_7 0x07
221 #define ROUTER_CS_9 0x09
222 #define ROUTER_CS_25 0x19
223 #define ROUTER_CS_26 0x1a
224 #define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0)
232 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
233 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
234 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
235 USB4_SWITCH_OP_NVM_WRITE = 0x20,
236 USB4_SWITCH_OP_NVM_AUTH = 0x21,
237 USB4_SWITCH_OP_NVM_READ = 0x22,
238 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
239 USB4_SWITCH_OP_DROM_READ = 0x24,
240 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
241 USB4_SWITCH_OP_BUFFER_ALLOC = 0x33,
245 #define TMU_RTR_CS_0 0x00
249 #define TMU_RTR_CS_1 0x01
252 #define TMU_RTR_CS_2 0x02
253 #define TMU_RTR_CS_3 0x03
254 #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
257 #define TMU_RTR_CS_15 0x0f
258 #define TMU_RTR_CS_15_FREQ_AVG_MASK GENMASK(5, 0)
262 #define TMU_RTR_CS_18 0x12
264 #define TMU_RTR_CS_22 0x16
265 #define TMU_RTR_CS_24 0x18
266 #define TMU_RTR_CS_25 0x19
269 TB_TYPE_INACTIVE = 0x000000,
270 TB_TYPE_PORT = 0x000001,
271 TB_TYPE_NHI = 0x000002,
272 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
273 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */
274 TB_TYPE_DP_HDMI_IN = 0x0e0101,
275 TB_TYPE_DP_HDMI_OUT = 0x0e0102,
276 TB_TYPE_PCIE_DOWN = 0x100101,
277 TB_TYPE_PCIE_UP = 0x100102,
278 TB_TYPE_USB3_DOWN = 0x200101,
279 TB_TYPE_USB3_UP = 0x200102,
284 /* DWORD 0 */
314 #define ADP_CS_4 0x04
315 #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
319 #define ADP_CS_5 0x05
325 #define TMU_ADP_CS_3 0x03
327 #define TMU_ADP_CS_6 0x06
329 #define TMU_ADP_CS_8 0x08
330 #define TMU_ADP_CS_8_REPL_TIMEOUT_MASK GENMASK(14, 0)
333 #define TMU_ADP_CS_9 0x09
334 #define TMU_ADP_CS_9_REPL_N_MASK GENMASK(7, 0)
339 #define LANE_ADP_CS_0 0x00
344 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL 0x2
348 #define LANE_ADP_CS_1 0x01
349 #define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0)
350 #define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc
353 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
354 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
356 #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX 0x1
357 #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX 0x2
358 #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL 0x0
366 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
367 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
368 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN4 0x2
374 #define PORT_CS_1 0x01
383 #define PORT_CS_2 0x02
384 #define PORT_CS_18 0x12
393 #define PORT_CS_19 0x13
394 #define PORT_CS_19_DPR BIT(0)
403 #define ADP_DP_CS_0 0x00
408 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
411 #define ADP_DP_CS_2 0x02
412 #define ADP_DP_CS_2_NRD_MLC_MASK GENMASK(2, 0)
419 #define ADP_DP_CS_2_GR_0_25G 0x0
420 #define ADP_DP_CS_2_GR_0_5G 0x1
421 #define ADP_DP_CS_2_GR_1G 0x2
429 #define ADP_DP_CS_3 0x03
431 #define DP_LOCAL_CAP 0x04
432 #define DP_REMOTE_CAP 0x05
434 #define DP_STATUS 0x06
438 #define DP_STATUS_CTRL 0x06
441 #define DP_COMMON_CAP 0x07
443 #define ADP_DP_CS_8 0x08
444 #define ADP_DP_CS_8_REQUESTED_BW_MASK GENMASK(7, 0)
454 #define DP_COMMON_CAP_RATE_RBR 0x0
455 #define DP_COMMON_CAP_RATE_HBR 0x1
456 #define DP_COMMON_CAP_RATE_HBR2 0x2
457 #define DP_COMMON_CAP_RATE_HBR3 0x3
460 #define DP_COMMON_CAP_1_LANE 0x0
461 #define DP_COMMON_CAP_2_LANES 0x1
462 #define DP_COMMON_CAP_4_LANES 0x2
470 #define ADP_DP_CS_8 0x08
475 #define ADP_PCIE_CS_0 0x00
477 #define ADP_PCIE_CS_1 0x01
478 #define ADP_PCIE_CS_1_EE BIT(0)
481 #define ADP_USB3_CS_0 0x00
484 #define ADP_USB3_CS_1 0x01
485 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
489 #define ADP_USB3_CS_2 0x02
490 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
494 #define ADP_USB3_CS_3 0x03
495 #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)
496 #define ADP_USB3_CS_4 0x04
499 #define ADP_USB3_CS_4_MSLR_20G 0x1
503 /* DWORD 0 */
530 #define TB_TIME_VSEC_3_CS_9 0x9
532 #define TB_TIME_VSEC_3_CS_26 0x1a
551 #define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b
552 #define TB_PLUG_EVENTS_PCIE_CMD 0x1c
553 #define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0)
557 #define TB_PLUG_EVENTS_PCIE_CMD_WR 0x1
560 #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL 0x2
563 #define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA 0x1d
566 #define TB_LOW_PWR_C1_CL1 0x1
571 #define TB_LOW_PWR_C3_CL1 0x3
574 #define TB_LC_DESC 0x02
575 #define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
580 #define TB_LC_FUSE 0x03
581 #define TB_LC_SNK_ALLOCATION 0x10
582 #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
583 #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
586 #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
587 #define TB_LC_POWER 0x740
590 #define TB_LC_PORT_MODE 0x26
591 #define TB_LC_PORT_MODE_DPR BIT(0)
593 #define TB_LC_CS_42 0x2a
596 #define TB_LC_PORT_ATTR 0x8d
599 #define TB_LC_SX_CTRL 0x96
613 #define TB_LC_LINK_ATTR 0x97
616 #define TB_LC_LINK_REQ 0xad